Liquid crystal display device and manufacturing method thereof

ABSTRACT

A photolithography step and an etching step for forming an island-shaped semiconductor layer is omitted, and a liquid crystal display device is manufactured through the following four photolithography steps: a step for forming a gate electrode (including a wiring or the like formed from the same layer), a step for forming a source electrode and a drain electrode (including a wiring or the like formed from the same layer), a step for forming a contact hole (including removal of an insulating layer or the like in a region other than the contact hole), and a step for forming a pixel electrode (including a wiring or the like formed from the same layer). In the step of forming the contact hole, a groove portion in which the semiconductor layer is removed is formed, so that formation of parasitic channels is prevented.

TECHNICAL FIELD

The present invention relates to a semiconductor device, a liquid crystal display device, a manufacturing method of the semiconductor device, and a manufacturing method of the liquid crystal display device.

In this specification, a semiconductor device means all types of devices that can function by utilizing semiconductor characteristics, and a transistor, a semiconductor circuit, a memory device, an imaging device, a display device, an electro-optical device, an electronic device, and the like are all semiconductor devices.

BACKGROUND ART

In recent years, transistors that are formed using a semiconductor thin film having a thickness of several nanometers to several hundreds of nanometers over a substrate having an insulating surface such as a glass substrate have been attracting attentions. Transistors are widely used for electronic devices such as ICs (integrated circuits) and electro-optical devices. In particular, transistors are urgently developed as switching elements of image display devices typified by liquid crystal display devices and the like. In an active matrix liquid crystal display device, a voltage is applied between a pixel electrode connected to a selected switching element and an opposite electrode corresponding to the pixel electrode, and thus, a liquid crystal layer disposed between the pixel electrode and the opposite electrode is modulated optically. The optical modulation can be recognized as a display pattern by an observer. An active matrix liquid crystal display device here means a liquid crystal display device which employs a method in which a display pattern is formed on a screen by driving pixel electrodes arranged in matrix using switching elements.

The range of uses of such an active matrix liquid crystal display device is expanding, and demands for larger screen size, higher definition, and higher aperture ratio are increasing. In addition, it is demanded that the active matrix liquid crystal display device has high reliability and that a production method of the active matrix liquid crystal display device offers high yield and reduces production cost. Simplification of a process is one way for increasing productivity and reducing production cost.

In active matrix liquid crystal display devices, transistors are mainly used as switching elements. In manufacturing transistors, reduction in the number of photolithography steps or simplification of the photolithography step is important for simplification of the whole process. For example, when one photolithography step is added, the following steps are further needed: resist application, prebaking, light exposure, development, postbaking, and the like and, moreover, steps before and after the aforementioned steps, such as film formation, etching, resist removal, cleaning, drying, and the like. The number of steps is significantly increased only by adding one photolithography step in the manufacturing process. Therefore, many techniques for reducing the number of photolithography steps or simplifying the photolithography step in a manufacturing process have been developed.

Transistors are broadly classified into top-gate transistors, in which a channel formation region is provided below a gate electrode, and bottom-gate transistors, in which a channel formation region is provided above a gate electrode. These transistors are generally manufactured using at least five photomasks.

Many conventional techniques for simplifying the photolithography step use a complicated technique such as backside light exposure, resist reflow, or a lift-off method, which requires a special apparatus in many cases. Using such complicated techniques may cause various problems, thereby leading to reduction in yield. Moreover, electrical characteristics of transistors are often deteriorated.

As typical means for simplifying the photolithography step in a manufacturing process of a transistor, a technique using a multi-tone mask (called a half-tone mask or a gray-tone mask) is widely known. As a technique for reducing the number of manufacturing steps by using a multi-tone mask, Patent Document 1 can be, for example, given.

REFERENCE Patent Document

-   [Patent Document 1] Japanese Published Patent Application No.     2003-179069

DISCLOSURE OF INVENTION

An object of one embodiment of the present invention is to reduce the number of photolithography steps used for manufacturing a transistor to less than the conventional one.

An object of one embodiment of the present invention is to reduce the number of photomasks used for manufacturing a display device including a thin film transistor to less than the conventional one.

An object of one embodiment of the present invention is to provide a liquid crystal display device at low cost with high productivity.

An object of one embodiment of the present invention is to provide a liquid crystal display device with low power consumption.

An object of one embodiment of the present invention is to provide a liquid crystal display device with high reliability.

A photolithography step and an etching step for forming an island-shaped semiconductor layer is omitted, and a semiconductor device used in a liquid crystal display device is manufactured through the following four photolithography steps: a step for forming a gate electrode (including a wiring formed from the same layer), a step for forming a source electrode and a drain electrode (including a wiring formed from the same layer), a step for forming a contact hole (including removal of an insulating layer or the like in a region other than the contact hole), and a step for forming a pixel electrode (including a wiring or the like formed from the same layer).

In this case, since a photolithography step and an etching step for forming an island-shaped semiconductor layer are not performed, a semiconductor layer remains also in a region other than the region where a transistor is to be formed. As a result, for example, a channel may be formed in the semiconductor layer in a region overlapping with the pixel electrode, depending on the potential supplied to the pixel electrode. Note that a channel formed in a place where the channel is not essentially necessary in the above-described manner is called a parasitic channel.

For example, in the case where a parasitic channel is formed in a semiconductor layer overlapping with a pixel electrode in a first pixel among a plurality of pixels, a wiring included in the first pixel and a wiring included in a second pixel that is adjacent to the first pixel may be electrically connected to each other through the parasitic channel. In other words, the pixel electrode included in the first pixel functions as a gate electrode, the wiring included in the first pixel functions as one of a source electrode and a drain electrode, and the wiring included in the second pixel functions as the other of the source electrode and the drain electrode. A transistor obtained by formation of a channel in a place where the channel is not essentially necessary in the above-described manner is called a parasitic transistor.

In the case where the distance between adjacent wirings is short, even without a layer functioning as a gate electrode, a parasitic channel may be formed between the adjacent wirings and the adjacent wirings may be electrically connected to each other.

When a parasitic channel or a parasitic transistor is formed, interference of signals between the wirings occurs and it becomes difficult to transmit an accurate signal.

In order to avoid the influence of formation of a parasitic channel or a parasitic transistor, a groove portion is formed along a second wiring that is electrically connected to the source electrode. The groove portion is formed so as to cross at least a portion of a first wiring, which is electrically connected to the gate electrode, in the line width direction of the first wiring across both edges thereof. The groove portion is formed so as to cross at least a portion of a capacitor wiring in the line width direction of the capacitor wiring across both edges thereof. The groove portion is formed so as to extend beyond edges of the pixel electrode in a direction parallel to a direction in which the second wiring extends. The groove portion and the pixel electrode may or may not overlap with each other.

The formation of the groove portion is performed at the same time as the formation of the contact hole in the step for forming the contact hole, and the semiconductor layer is removed in the groove portion. In other words, the semiconductor layer does not exist at least on the bottom surface of the groove portion.

One embodiment of the present invention includes a transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer; a first wiring electrically connected to the gate electrode; a second wiring electrically connected to the source electrode; a pixel electrode electrically connected to the drain electrode; a capacitor wiring; and a groove portion. The semiconductor layer overlaps with the first wiring, the second wiring, the pixel electrode, and the capacitor wiring. The groove portion is formed over at least a part of the first wiring and over at least a part of the capacitor wiring. Further, the groove portion is formed along the second wiring so as to extend beyond edges of the pixel electrode in a direction parallel to a direction in which the second wiring extends.

By formation of the groove portion in which the semiconductor layer is removed, formation of parasitic transistors can be prevented.

The groove portion formed over the first wiring (also referred to as a first groove portion), the groove portion formed over the capacitor wiring (also referred to as a second groove portion), and the groove portion formed so as to extend beyond the edges of the pixel electrode (also referred to as a third groove portion) may be formed individually, or a structure in which one groove portion serves as plural groove portions among the first to third groove portions may be employed.

Although the size of the groove portion is not particularly limited, for surely preventing formation of a parasitic transistor, the distance of the portion where the semiconductor layer is removed in the groove portion in a direction perpendicular to the direction in which the second wiring extends is preferably 1 μm or more, further preferably 2 μm or more.

One embodiment of the present invention includes the steps of: forming a gate electrode, a first wiring electrically connected to the gate electrode, and a capacitor wiring over a substrate by a first photolithography step; forming a gate insulating layer over the gate electrode, the first wiring, and the capacitor wiring; forming a semiconductor layer over the gate insulating layer; forming a source electrode and a drain electrode over the semiconductor layer by a second photolithography step; forming an insulating layer over the source electrode and the drain electrode; by a third photolithography step, forming a contact hole by selectively removing part of the insulating layer overlapping with the drain electrode, and removing at least part of the semiconductor layer over the first wiring and at least part of the semiconductor layer over the capacitor wiring; and forming a pixel electrode over the insulating layer by a fourth photolithography step.

An insulating layer having a function of preventing diffusion of an impurity element from the substrate may be provided between the substrate and the gate electrode.

According to one embodiment of the present invention, a first insulating layer is formed over a substrate; a first electrode is formed over the first insulating layer; a second insulating layer is formed over the first electrode; a semiconductor layer is formed over the second insulating layer; a third electrode and a fourth electrode are formed over the semiconductor layer; and a third insulating layer is formed to cover the third electrode and the fourth electrode. Formation of a contact hole by removing part of the third insulating layer overlapping with the third electrode or the fourth electrode and removal of part of the third insulating layer, part of the semiconductor layer, and part of the second insulating layer are performed in the same step.

The second insulating layer functions as a gate insulating layer, and the third insulating layer functions as a protective insulating layer. Further, the first electrode functions as a gate electrode, the third electrode functions as one of a source electrode and a drain electrode, and the fourth electrode functions as the other of the source electrode and the drain electrode.

The formation of the contact hole and the removal of the part of the third insulating layer, the part of the semiconductor layer, and the part of the second insulating layer can be performed by dry etching, wet etching, or a combination of dry etching and wet etching.

When the gate electrodes, the source electrodes, the drain electrodes, or a wiring connected to such electrodes are formed of a material containing copper or aluminum, wiring resistance can be reduced and thus signal delay can be prevented.

Using an oxide semiconductor for the semiconductor layer can realize a liquid crystal display device with low power consumption and high reliability.

Note that an oxide semiconductor which is purified (purified OS) by reduction of an impurity such as moisture or hydrogen which serves as an electron donor (donor) can be made to be an i-type (intrinsic) oxide semiconductor or an oxide semiconductor extremely close to an i-type semiconductor (a substantially i-type oxide semiconductor) by supplying oxygen to the oxide semiconductor to reduce oxygen deficiency in the oxide semiconductor. A transistor including the i-type or substantially i-type oxide semiconductor has a characteristic of very small off-state current. Specifically, the concentration of hydrogen in the purified oxide semiconductor which is measured by secondary ion mass spectrometry (SIMS) is less than or equal to 5×10¹⁹/cm³, preferably less than or equal to 5×10¹⁸/cm³, further preferably less than or equal to 5×10¹⁷/cm³, still further preferably less than or equal to 1×10¹⁶/cm³.

In addition, the carrier density of the i-type or substantially i-type oxide semiconductor, which is measured by Hall effect measurement, is less than 1×10¹⁴/cm³, preferably less than 1×10¹²/cm³, further preferably less than 1×10¹¹/cm³. Furthermore, the band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, further preferably 3 eV or more. With the use of the i-type or substantially i-type oxide semiconductor, the off-state current of the transistor can be reduced.

The analysis of the hydrogen concentration in the oxide semiconductor by SIMS is described here. It is known to be difficult to obtain accurate data in the proximity of a surface of a sample or in the proximity of an interface between stacked films formed of different materials by the SIMS analysis in principle. Thus, in the case where the distribution of the hydrogen concentration in the thickness direction of a film is analyzed by SIMS, the average value of the hydrogen concentration in a region of the film where almost the same value can be obtained without significant variation is employed as the hydrogen concentration. Further, in the case where the thickness of the film is small, a region where almost the same value can be obtained cannot be found in some cases due to the influence of the hydrogen concentration of an adjacent film. In this case, the maximum value or the minimum value of the hydrogen concentration of a region where the film is provided is employed as the hydrogen concentration of the film. Furthermore, in the case where a maximum value peak and a minimum value valley do not exist in the region where the film is provided, the value of the inflection point is employed as the hydrogen concentration.

According to one embodiment of the present invention, the number of manufacturing steps of a liquid crystal display device can be reduced; accordingly, a liquid crystal display device can be provided at low cost with high productivity.

According to one embodiment of the present invention, a liquid crystal display device with low power consumption and high reliability can be provided.

One embodiment of the present invention solves at least one of the above problems.

BRIEF DESCRIPTION OF DRAWINGS

In the accompanying drawings:

FIG. 1 is a top view illustrating an embodiment of the present invention;

FIGS. 2A to 2D are cross-sectional views illustrating an embodiment of the present invention;

FIG. 3 is a top view illustrating an embodiment of the present invention;

FIGS. 4A to 4C are cross-sectional views illustrating an embodiment of the present invention;

FIGS. 5A and 5B are a top view and a cross-sectional view illustrating an embodiment of the present invention;

FIGS. 6A and 6B are circuit diagrams of an embodiment of the present invention;

FIGS. 7A1 and 7B1 and FIGS. 7A2 and 7B2 are top views and cross-sectional views, respectively, illustrating an embodiment of the present invention;

FIGS. 8A and 8B are a top view and a cross-sectional view illustrating an embodiment of the present invention;

FIGS. 9A to 9C are cross-sectional views illustrating an embodiment of the present invention;

FIGS. 10A to 10C are cross-sectional views illustrating an embodiment of the present invention;

FIGS. 11A to 11C are cross-sectional views illustrating an embodiment of the present invention;

FIGS. 12A and 12B are a top view and a cross-sectional view, respectively, illustrating an embodiment of the present invention;

FIGS. 13A and 13B are views illustrating an embodiment of the present invention;

FIGS. 14A to 14F are views illustrating examples of usage mode of an electronic appliance;

FIGS. 15A to 15E are views illustrating crystal structures of oxide materials;

FIGS. 16A to 16C are views illustrating a crystal structure of an oxide material;

FIGS. 17A to 17C are views illustrating a crystal structure of an oxide material;

FIGS. 18A and 18B are views illustrating crystal structures of oxide materials; and

FIGS. 19A and 19B are views illustrating a stacked structure of a groove portion of a semiconductor device.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the present invention is not limited to the following description, and it will be readily appreciated by those skilled in the art that the mode and details can be changed in various different ways without departing from the spirit and the scope of the present invention. Therefore, the present invention should not be construed as being limited to the following description of the embodiments. Note that in the structures of the present invention which are described below, the same reference numerals are commonly used to denote the same components or components having similar functions among different drawings, and description of such components is not repeated.

In addition, in this specification and the like, ordinal numbers such as “first”, “second”, and “third” are used in order to avoid confusion among components, and the terms do not limit the components numerically.

In addition, the position, size, range, or the like of each structure illustrated in drawings and the like is not accurately represented in some cases for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like as disclosed in the drawings and the like.

A transistor is one kind of semiconductor elements and can amplify current or voltage and perform a switching operation for controlling conduction or non-conduction, for example. A transistor in this specification includes an insulated-gate field effect transistor (IGFET) and a thin film transistor (TFT).

Functions of a “source” and a “drain” of a transistor might interchange when a transistor of opposite polarity is used or the direction of current flow is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be used to denote the drain and the source, respectively, in this specification.

In addition, in this specification and the like, the term such as “electrode” or “wiring” does not limit a function of a component. For example, an “electrode” is sometimes used as part of a “wiring”, and vice versa. Further, the term “electrode” or “wiring” can also mean a combination of a plurality of “electrodes” and “wirings” formed in an integrated manner.

Embodiment 1

In this embodiment, examples of a pixel configuration of a liquid crystal display device formed through a process in which the number of photomasks and the number of photolithography steps are reduced, and an example of a method for forming the pixel configuration will be described with reference to FIG. 1, FIGS. 2A to 2D, FIG. 3, FIGS. 4A to 4C, FIGS. 5A and 5B, FIGS. 6A and 6B, FIGS. 7A1, 7A2, 7B1, and 7B2, FIGS. 8A and 8B, FIGS. 9A to 9C, and FIGS. 10A to 10C.

FIG. 6A illustrates an example of the configuration of a semiconductor device 100 that is used in a liquid crystal display device. The semiconductor device 100 includes a pixel region 102, a terminal portion 103 including m terminals 105 (m is an integer of greater than or equal to 1), and a terminal portion 104 including n terminals 106 (n is an integer of greater than or equal to 1) over a substrate 101. Further, the semiconductor device 100 includes m wirings 212 electrically connected to the terminal portion 103, n wirings 216 electrically connected to the terminal portion 104, and a wiring 203. The pixel region 102 includes a plurality of pixels 110 arranged in a matrix of m (rows) and n (columns). A pixel 110(i,j) in the i-th row and the j-th column (i is an integer of greater than or equal to 1 and less than or equal to m, and j is an integer of greater than or equal to 1 and less than or equal to n) is electrically connected to a wiring 212-i and a wiring 216-j. In addition, each pixel is connected to the wiring 203 serving as a capacitor electrode or a capacitor wiring, and the wiring 203 is electrically connected to the terminal 107. The wiring 212-i is electrically connected to a terminal 105-i, and the wiring 216-j is electrically connected to a terminal 106-j.

The terminal portion 103 and the terminal portion 104 are external input terminals and are connected to external control circuits with flexible printed circuits (FPC) or the like. Signals supplied from the external control circuits are input to the semiconductor device 100 through the terminal portion 103 and the terminal portion 104. In FIG. 6A, such terminal portions 103 are provided on the right and left of the pixel region 102, so that signals are input from two directions. Further, such terminal portions 104 are provided above and below the pixel region 102, so that signals are input from two directions. By inputting signals from two directions, signal supply capability is increased and high-speed operation of the semiconductor device 100 is facilitated. In addition, influences of signal delay due to an increase in size of the semiconductor device 100 or an increase in wiring resistance accompanied by an increase in definition can be reduced. Moreover, the semiconductor device 100 can have redundancy, so that reliability of the semiconductor device 100 can be improved. Although two terminal portions 103 and two terminal portions 104 are provided in FIG. 6A, a structure in which one terminal portion 103 and one terminal portion 104 are provided may also be employed.

FIG. 6B illustrates a circuit configuration of the pixel 110. The pixel 110 includes a transistor 111, a liquid crystal element 112, and a capacitor 113. A gate electrode of the transistor 111 is electrically connected to the wiring 212-i, and one of a source electrode and a drain electrode of the transistor 111 is electrically connected to the wiring 216-j. The other of the source electrode and the drain electrode of the transistor 111 is electrically connected to one electrode of the liquid crystal element 112 and one electrode of the capacitor 113. The other electrode of the liquid crystal element 112 is electrically connected to an electrode 114. The potential of the electrode 114 may be a fixed potential such as 0 V, GND, or a common potential. The other electrode of the capacitor 113 is electrically connected to the wiring 203.

The transistor 111 has a function of selecting whether an image signal supplied from the wiring 216-j is input to the liquid crystal element 112. After a signal that turns on the transistor 111 is supplied to the wiring 212-i, an image signal is supplied to the liquid crystal element 112 from the wiring 216-j through the transistor 111. The transmittance of light is controlled in accordance with the image signal (potential) supplied to the liquid crystal element 112. The capacitor 113 has a function as a storage capacitor (also referred to as a Cs capacitor) for holding a potential supplied to the liquid crystal element 112. The capacitor 113 need not necessarily be provided; however, in the case of providing the capacitor 113, variation in the potential applied to the liquid crystal element 112, which is caused by a current flowing between a source electrode and a drain electrode in an off state of the transistor 111 (off-state current), can be suppressed.

For a semiconductor layer for forming a channel of the transistor 111, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used. Examples of a semiconductor material are silicon, germanium, silicon germanium, silicon carbide, and gallium arsenide. The display device described in this embodiment has a structure in which the semiconductor layer remains in the pixel region; thus, in the case where the display device including the semiconductor is used for a transmissive display device, the transmittance of visible light is preferably increased by, for example, thinning the semiconductor layer as much as possible.

Alternatively, an oxide semiconductor can be used for the semiconductor layer in which a channel of the transistor 111 is formed. An oxide semiconductor has an energy gap that is as wide as greater than or equal to 3.0 eV, and thus has high transmittance with respect to visible light. In a transistor obtained by processing an oxide semiconductor under appropriate conditions, the off-state current at ambient temperature (e.g., 25° C.) can be less than or equal to 100 zA (1×10⁻¹⁹ A), less than or equal to 10 zA (1×10⁻²⁰ A), and further less than or equal to 1 zA (1×10⁻²¹ A). Therefore, the potential applied to the liquid crystal element 112 can be held without provision of the capacitor 113. In addition, in teams of realizing a liquid crystal display device with low power consumption, it is preferable to use an oxide semiconductor layer for the semiconductor layer in which the channel of the transistor 111 is formed.

Next, an example of the configuration of the pixel 110 illustrated in FIGS. 6A and 6B will be described with reference to FIG. 1 and FIGS. 2A to 2D. FIG. 1 is a top view illustrating a plan structure of the pixel 110, and FIGS. 2A to 2D are cross-sectional views illustrating a stacked structure of the pixel 110. Note that chain lines A1-A2, B1-B2, C1-C2, and D1-D2 in FIG. 1 correspond to cross sections A1-A2, B1-B2, C1-C2, and D1-D2 in FIGS. 2A to 2D, respectively.

In the transistor 111 in this embodiment, a drain electrode 206 b is surrounded by a source electrode 206 a that is U-shaped (or C-shaped, square-bracket-like shaped, or horseshoe-shaped). With such a shape, an enough channel width can be ensured even when the area of the transistor is small, and accordingly, the amount of current flowing at the time of conduction of the transistor (also referred to as the on-state current) can be increased.

If parasitic capacitance generated between a gate electrode 202 and the drain electrode 206 b electrically connected to a pixel electrode 210 is large, the transistor is easily influenced by feedthrough, which may cause degradation in display quality because the potential supplied to the liquid crystal element 112 cannot be held accurately. With the structure in which the source electrode 206 a is U-shaped and surrounds the drain electrode 206 b as described in this embodiment, an enough channel width can be ensured and parasitic capacitance generated between the drain electrode 206 b and the gate electrode 202 can be reduced. Therefore, the display quality of a liquid crystal display device can be improved.

The wiring 203 functions as a capacitor electrode or a capacitor wiring. In this embodiment, the capacitor 113 is formed using the overlapping wiring 203 and drain electrode 206 b.

The semiconductor device described in this embodiment has a structure in which the semiconductor layer 205 remains in the entire pixel region because a photolithography step and an etching step for forming an island-shaped semiconductor layer are not performed in order to simplify the manufacturing process. Consequently, a first parasitic transistor in which the wiring 212-i functions as a gate electrode, the wiring 216-j functions as one of a source electrode and a drain electrode, and the wiring 216-j+1 functions as the other of the source electrode and the drain electrode is formed.

Further, a second parasitic transistor in which the wiring 203 functions as a gate electrode, the wiring 216-j functions as one of a source electrode and a drain electrode, and the wiring 216-j+1 functions as the other of the source electrode and the drain electrode is formed.

Furthermore, a third parasitic transistor in which the pixel electrode 210 functions as a gate electrode, an insulating layer 207 functions as a gate insulating layer, the wiring 216-j functions as one of a source electrode and a drain electrode, and the wiring 216-j+1 functions as the other of the source electrode and the drain electrode is formed.

When such a potential as to turn on the transistor 111 is supplied to the wiring 212-i, the first parasitic transistor is also turned on, and the wiring 216-j and the wiring 216-j+1 are electrically connected to each other. The electrical connection between the wiring 216-j and the wiring 216-j+1 by the first parasitic transistor causes interference of image signals therebetween; accordingly, it becomes difficult to supply accurate image signals to the liquid crystal element 112.

In the case where the second parasitic transistor functions as an n-channel transistor, when the potential of the wiring 216-j or the wiring 216-j+1 is lower than that supplied to the wiring 203 and the absolute value of the potential difference is larger than the threshold of the second parasitic transistor, a channel is formed in the semiconductor layer 205 located below the pixel electrode 210 and the second parasitic transistor is on.

When the second parasitic transistor is on, the wiring 216-j and the wiring 216-j+1 are electrically connected to each other. The electrical connection between the wiring 216-j and the wiring 216-j+1 by the second parasitic transistor causes interference of image signals therebetween; accordingly, it becomes difficult to supply accurate image signals to the liquid crystal element 112.

In the case where the third parasitic transistor functions as an n-channel transistor, when the potential of the wiring 216-j or the wiring 216-j+1 is lower than the potential supplied to the pixel electrode 210 or the potential held at the pixel electrode 210 and the absolute value of the potential difference is larger than the threshold of the third parasitic transistor, a channel is formed in the semiconductor layer 205 located below the pixel electrode 210 and the third parasitic transistor is on.

When the third parasitic transistor is on, the wiring 216-j and the wiring 216-j+1 are electrically connected to each other. The electrical connection between the wiring 216-j and the wiring 216-j+1 by the third parasitic transistor causes interference of image signals therebetween; accordingly, it becomes difficult to supply accurate image signals to the liquid crystal element 112. When the pixel electrode 210 is formed close to the wiring 216-j or the wiring 216-j+1 for the purpose of increasing the pixel aperture ratio or the like, the influence of the third parasitic transistor is increased.

In view of this, a structure in which a groove portion 230 in which the semiconductor layer 205 is removed is provided in the pixel 110 so that the above-described parasitic transistors are not formed is employed in this embodiment. The groove portion 230 is provided so as to cross the wiring 212-i in the line width direction of the wiring 212-i across both edges thereof; in this way, formation of the first parasitic transistor can be prevented. In addition, the groove portion 230 is provided so as to cross the wiring 203 in the line width direction of the wiring 203 across both edges thereof; in this way, formation of the second parasitic transistor can be prevented. Note that a plurality of groove portions 230 may be provided over the wiring 212-i, and a plurality of groove portions 230 may be provided over the wiring 203.

Furthermore, the groove portion 230 is formed at least between the wiring 216-j and the pixel electrode 210 or between the wiring 216-j+1 and the pixel electrode 210, along a direction parallel to the direction in which the wiring 216-j or the wiring 216-j+1 extends, so as to extend beyond an edge 231 and an edge 232 of the pixel electrode 210. In this way, formation of the third parasitic transistor can be prevented. The groove portion 230 is not necessarily provided in parallel to the wiring 216-j or the wiring 216-j+1 and may have a flection portion or a bending portion.

In FIG. 1, the groove portions 230 are separated in a region between the wiring 212-i and the wiring 203. However, the groove portion 230 provided to cross the wiring 212-i in the line width direction of the wiring 212-i across the both edges thereof may be extended and connected to the groove portion 230 provided to cross the wiring 203 in the line width direction of the wiring 203 across the both edges thereof.

It is also possible to prevent formation of the second parasitic transistor without providing the groove portion 230 over the wiring 203 by setting the potential of the wiring 203 to be lower than the potential supplied to the wiring 216-j or the wiring 216-j+1. However in this case, a power supply for supplying the above-described potential to the wiring 203 needs to be provided additionally.

Although the size of the groove portion 230 in which the semiconductor layer 205 is removed is not particularly limited, for surely preventing formation of a parasitic transistor, the distance of the portion where the semiconductor layer is removed in the groove portion 230 in a direction perpendicular to the direction in which the wiring 216-j or the wiring 216-j+1 extends is preferably 1 μm or more, further preferably 2 μm or more.

The cross section A1-A2 shows the stacked structure of the transistor 111 and the stacked structure of the capacitor 113. The transistor 111 is a bottom-gate transistor. The cross section B1-B2 shows the stacked structure from the wiring 216-j to the wiring 216-j+1, including the pixel electrode 210 and the groove portion 230. Further, the cross section C1-C2 shows the stacked structure of an intersection of the wiring 216-j and the wiring 212-i. The cross section D1-D2 shows the stacked structure of an intersection of the wiring 216-j+1 and the wiring 212-i and the stacked structure of the groove portion 230.

In the cross section A1-A2 in FIG. 2A, a base layer 201 is formed over a substrate 200, and the gate electrode 202 and the wiring 203 are formed over the base layer 201. Over the gate electrode 202 and the wiring 203, a gate insulating layer 204 and a semiconductor layer 205 are formed. Over the semiconductor layer 205, the source electrode 206 a and the drain electrode 206 b are formed. Further, an insulating layer 207 is formed over the source electrode 206 a and the drain electrode 206 b so as to be in contact with part of the semiconductor layer 205. The pixel electrode 210 is formed over the insulating layer 207 and is electrically connected to the drain electrode 206 b through a contact hole 208 formed in the insulating layer 207.

A portion in which the wiring 203 and the drain electrode 206 b overlap with each other with the gate insulating layer 204 and the semiconductor layer 205 interposed therebetween functions as the capacitor 113. The gate insulating layer 204 and the semiconductor layer 205 function as a dielectric layer. In the case where a multi-layer dielectric layer is formed between the wiring 203 and the pixel electrode 210, even when a pinhole is generated in one dielectric layer, the pinhole is covered with another dielectric layer; accordingly, the capacitor 113 can operate normally. The relative permittivity of an oxide semiconductor is as high as 14 to 16. When the oxide semiconductor is used for the semiconductor layer 205, the capacitance value of the capacitor 113 can be increased.

In the cross section B1-B2 illustrated in FIG. 2B, the base layer 201 is formed over the substrate 200, the gate insulating layer 204 is formed over the base layer 201, and the semiconductor layer 205 is formed over the gate insulating layer 204. The wiring 216-j and the wiring 216-j+1 are formed over the semiconductor layer 205, and the insulating layer 207 is formed over the semiconductor layer 205, the wiring 216-j, and the wiring 216-j+1. The pixel electrode 210 is formed over the insulating layer 207.

The groove portion 230 is formed between the wiring 216-j+1 and the pixel electrode 210 by removing part of the gate insulating layer 204, part of the semiconductor layer 205, and part of the insulating layer 207. The groove portion 230 does not include a semiconductor layer at least on its bottom surface.

In the cross section C1-C2 illustrated in FIG. 2C, the base layer 201 is formed over the substrate 200, and the wiring 212-i is formed over the base layer 201. Over the wiring 212-i, the gate insulating layer 204 and the semiconductor layer 205 are formed. The wiring 216-j is formed over the semiconductor layer 205, and the insulating layer 207 is formed over the wiring 216-j.

In the cross section D1-D2 illustrated in FIG. 2D, the base layer 201 is formed over the substrate 200, and the wiring 212-i is formed over the base layer 201. Further, the gate insulating layer 204 and the semiconductor layer 205 are formed over the wiring 212-i. The wiring 216-j+1 is formed over the semiconductor layer 205, and the insulating layer 207 is formed over the wiring 216-j+1. In addition, the groove portion 230 is formed by removing part of the gate insulating layer 204, part of the semiconductor layer 205, and part of the insulating layer 207.

Next, an example of the pixel configuration, which is different from that illustrated in FIG. 1 will be described with reference to FIG. 3 and FIGS. 4A to 4C. FIG. 3 is a top view illustrating a plan structure of a pixel 120. Cross sections A1-A2, E1-E2, and F1-F2 in FIGS. 4A to 4C correspond to cross sections of portions indicated by chain lines A1-A2, E1-E2, and F1-F2 in FIG. 3. The pixel 120 illustrated in FIG. 3 is different from the pixel 110 illustrated in FIG. 1 in the structure of the groove portion 230. Note that the structure of the portion indicated by the chain line A1-A2 in FIG. 3 is the same as that in FIG. 1 and FIG. 2A.

The pixel 120 has a structure in which the groove portion 230 is provided between the wiring 216-j and the pixel electrode 210 and between the wiring 216-j+1 and the pixel electrode 210. The groove portion 230 is provided to not only cross the wiring 212-i and the wiring 203 in the line width direction of the wiring 212-i and the wiring 203 across the both edges thereof but also to exist in the region between the wiring 212-i and the wiring 203. By making the area of the groove portion 230 larger, formation of parasitic transistors can be prevented more surely.

Next, an example of the pixel configuration, which is different from those in FIG. 1, FIGS. 2A to 2D, FIG. 3, and FIGS. 4A to 4C, will be described with reference to FIGS. 5A and 5B. FIG. 5A is a top view illustrating a plan structure of a pixel 130. A cross section G1-G2 in FIG. 5B corresponds to a cross section of a portion indicated by a chain line G1-G2 in FIG. 5A. FIGS. 5A and 5B illustrate an example of the pixel configuration, in which the pixel 130 has a configuration which can be applied to a reflective liquid crystal display device by using a conductive layer with high light reflectance for the pixel electrode 211.

In the pixel 130, a groove portion 251 and a groove portion 252 in which the semiconductor layer 205 is removed are provided so as to cross the wiring 212-i in the line width direction of the wiring 212-i across the both edges thereof. When a plurality of groove portions which cross the wiring 212-i in the line width direction of the wiring 212-i across the both edges thereof is provided, the influence of a parasitic channel formed by the overlap with the wiring 212-i can be reduced more surely.

In the pixel 130, a groove portion 253 and a groove portion 254 in which the semiconductor layer 205 is removed are provided so as to cross the wiring 203 in the line width direction of the wiring 203 across the both edges thereof. When a plurality of groove portions which cross the wiring 203 in the line width direction of the wiring 203 across the both edges thereof is provided, the influence of a parasitic channel formed by the overlap with the wiring 203 can be reduced more surely.

Further in the pixel 130, a groove portion 255 and a groove portion 256 in which the semiconductor layer 205 is removed are provided along a direction parallel to the direction in which the wiring 216-j or the wiring 216-j+1 extends, so as to extend beyond an edge 233 and an edge 234 of the pixel electrode 211. When a plurality of groove portions is provided along a direction parallel to the direction in which the wiring 216-j or the wiring 216-j+1 extends so as to extend beyond the edge 233 and the edge 234 of the pixel electrode 211, the influence of a parasitic channel formed by the overlap with the pixel electrode 211 can be reduced more surely. The groove portion 255 and the groove portion 256 are not necessarily provided in parallel to the wiring 216-j or the wiring 216-j+1 and may have a flection portion or a bending portion.

The groove portion 255 and the groove portion 256 in the pixel 130 each have a bending portion, and part of the groove portion 255 and part of the groove portion 256 overlap with the pixel electrode 211. The pixel 130 includes a groove portion 257 and a groove portion 258 formed to overlap with the pixel electrode 211. By providing the groove portions 255 to 258 in this manner so as to overlap with the pixel electrode 211, a surface of the pixel electrode 211 can be uneven. By the uneven surface of the pixel electrode 211, incident light from the external is reflected diffusely, whereby more favorable display can be performed. As a result, visibility of display is improved.

It is preferable that the groove portions 255 to 258 formed to overlap with the pixel electrode 211 have a tapered side surface because coverage with the pixel electrode 211 is increased.

Next, examples of the structures of the terminal 105 and the terminal 106 will be described with reference to FIGS. 7A1, 7A2, 7B1, and 7B2. FIGS. 7A1 and 7A2 are a top view and a cross-sectional view, respectively, of the terminal 105. A chain line J1-J2 in FIG. 7A1 corresponds to a cross section J1-J2 in FIG. 7A2. FIGS. 7B1 and 7B2 are a top view and a cross-sectional view, respectively, of the terminal 106. A chain line K1-K2 in FIG. 7B1 corresponds to a cross section K1-K2 in FIG. 7B2. In the cross sections J1-J2 and K1-K2, J2 and K2 correspond to end portions of the substrate.

In the cross section J1-J2, the base layer 201 is formed over the substrate 200, and the wiring 212 is formed over the baser layer 201. The gate insulating layer 204, the semiconductor layer 205, and the insulating layer 207 are formed over the wiring 212. An electrode 221 is formed over the insulating layer 207, and the electrode 221 is electrically connected to the wiring 212 through a contact hole 219 formed in the gate insulating layer 204, the semiconductor layer 205, and the insulating layer 207.

In the cross section K1-K2, the base layer 201, the gate insulating layer 204, and the semiconductor layer 205 are formed over the substrate 200. The wiring 216 is formed over the semiconductor layer 205, and the insulating layer 207 is formed over the wiring 216. An electrode 222 is formed over the insulating layer 207, and the electrode 222 is electrically connected to the wiring 216 through a contact hole 220 formed in the insulating layer 207.

Note that the terminal 107 can have a structure similar to that of the terminal 105 or the terminal 106.

The pixel region 102 and the terminal portion 104 are connected with n wirings 216. In the case where the wirings 216 extending from the pixel region 102 to the terminals 106 in the terminal portion 104 are located close to each other, a parasitic channel may be formed in a portion of the semiconductor layer 205, which is between the adjacent wirings 216, due to the potential difference between the adjacent wirings 216, and therefore the adjacent wirings 216 may be electrically connected to each other.

This phenomenon can be prevented by providing a conductive layer over the entire region from the pixel region 102 to the terminal portion 104 or between the adjacent wirings 216 with an insulating layer provided between the conductive layer and the semiconductor layer 205 and by setting the potential of the conductive layer to such a potential as not to form a parasitic channel in the semiconductor layer 205.

For example, since most of oxide semiconductors tend to be n-type semiconductors, in the case of using an oxide semiconductor for the semiconductor layer 205, the potential of the conductive layer is set to a potential that is lower than the potential supplied to the wirings 216.

Further, it is also possible to prevent electrical connection between the adjacent wirings 216 by removing the semiconductor layer 205 between the adjacent wirings 216 in a step for forming a contact hole that is to be described later.

FIGS. 8A and 8B illustrate a structure in which the semiconductor layer 205 is removed by formation of groove portions 240 between the adjacent wirings 216. FIG. 8A is a top view illustrating a plan structure of the wirings 216 which are connected to the terminals 106. A cross section L1-L2 illustrated in FIG. 8B corresponds to a cross section in a portion indicated by a chain line L1-L2 in FIG. 8A. In FIG. 8A, the wiring 216-j is connected to the terminal 106-j, the wiring 216-j+1 is connected to the terminal 106-j+1, and the wiring 216-j+2 is connected to the terminal 106-j+2. Note that the groove portions 240 can be formed in a manner similar to that of the groove portions 230.

The groove portion 240 in which the semiconductor layer 205 is removed is formed between the adjacent wirings 216-j and 216-j+1. The groove portion 240 in which the semiconductor layer 205 is removed is formed between the adjacent wirings 216-j+1 and 216-j+2. By providing the groove portions 240 in which the semiconductor layer 205 is removed between the adjacent wirings 216, electrical connection between the adjacent wirings 216 can be prevented.

Although the size of the groove portion 240 in which the semiconductor layer 205 is removed is not particularly limited, for surely preventing formation of a parasitic channel, the distance of the portion where the semiconductor layer is removed in the groove portion 240 in a direction perpendicular to the direction in which the wiring 216-j or the wiring 216-j+1 extends is preferably 1 μm or more, further preferably 2 μm or more.

Then, a manufacturing method of the pixel portion of the liquid crystal display device described with reference to FIG. 1 will be described with reference to FIGS. 9A to 9C and FIGS. 10A to 10C. Note that cross sections A1-A2, J1-J2, and K1-K2 in FIGS. 9A to 9C and FIGS. 10A to 10C are cross-sectional views of the portions taken along the chain lines A1-A2, J1-J2, and K1-K2 in FIG. 1 and FIGS. 7A1, 7A2, 7B1, and 7B2, respectively.

First, an insulating layer to be the base layer 201 is formed with a thickness of greater than or equal to 50 nm and less than or equal to 300 nm, preferably greater than or equal to 100 nm and less than or equal to 200 nm over the substrate 200. As the substrate 200, as well as a glass substrate or a ceramic substrate, a plastic substrate or the like having heat resistance to withstand a process temperature in this manufacturing process can be used. In the case where a substrate does not need a light-transmitting property, a metal substrate such as a stainless alloy substrate, whose surface is provided with an insulating layer, may be used. As the glass substrate, for example, an alkali-free glass substrate of barium borosilicate glass, aluminoborosilicate glass, aluminosilicate glass, or the like may be used. In addition, a quartz substrate, a sapphire substrate, or the like can be used. Further, as the substrate 200, a glass substrate with any of the following sizes can be used: the 3rd generation (550 mm×650 mm), the 3.5th generation (600 mm×720 mm or 620 mm×750 mm), the 4th generation (680×880 mm or 730 mm×920 mm), the 5th generation (1100 mm×1300 mm), the 6th generation (1500 mm×1850 mm), the 7th generation (1870 mm×2200 mm), the 8th generation (2200 mm×2400 mm), the 9th generation (2400 mm×2800 mm or 2450 mm×3050 mm), and the 10th generation (2950 mm×3400 mm). In this embodiment, a substrate of aluminoborosilicate glass is used as the substrate 200.

The base layer 201 can be formed with a single-layer structure or a layered structure using one or more of the following insulating layers: an aluminum nitride layer, an aluminum oxynitride layer, a silicon nitride layer, a silicon oxide layer, a silicon nitride oxide layer, and a silicon oxynitride layer. The base layer 201 has a function of preventing diffusion of impurity elements from the substrate 200. Note that in this specification, silicon nitride oxide contains more nitrogen than oxygen and, in the case where measurements are performed using RBS and HFS, contains oxygen, nitrogen, silicon, and hydrogen at concentrations of greater than or equal to 5 at. % and less than or equal to 30 at. %, greater than or equal to 20 at. % and less than or equal to 55 at. %, greater than or equal to 25 at. % and less than or equal to 35 at. %, and greater than or equal to 10 at. % and less than or equal to 30 at. %, respectively. The base layer 201 can be Ruined by a sputtering method, a CVD method, a coating method, a printing method, or the like as appropriate.

In this embodiment, a stack of layers of silicon nitride and silicon oxide is used as the base layer 201. Specifically, a layer of silicon nitride is formed with a thickness of 50 nm over the substrate 200, and a layer of silicon oxide is formed with a thickness of 150 nm over the layer of silicon nitride. Note that the base layer 201 may be doped with phosphorus (P) or boron (B).

When a halogen element such as chlorine or fluorine is contained in the base layer 201, a function of preventing diffusion of impurity elements from the substrate 200 can be further improved. The peak of the concentration of a halogen element contained in the base layer 201 may be higher than or equal to 1×10¹⁵/cm³ and lower than or equal to 1×10²⁰/cm³ when measured by secondary ion mass spectrometry (SIMS).

Alternatively, gallium oxide may be used for the base layer 201. Further alternatively, a layered structure including a layer of gallium oxide and the above insulating layer may be used for the base layer 201. Gallium oxide is a material which is hardly charged; therefore, variation in threshold voltage due to charge buildup of the insulating layer can be suppressed.

Next, over the base layer 201, a conductive layer is formed with a thickness of greater than or equal to 100 nm and less than or equal to 500 nm, preferably greater than or equal to 200 nm and less than or equal to 300 nm by a sputtering method, a vacuum evaporation method, or a plating method, a resist mask is formed by a first photolithography step, and the conductive layer is selectively removed by etching, whereby the gate electrode 202, the wiring 203, and the wiring 212 are formed.

The conductive layer for forming the gate electrode 202, the wiring 203, and the wiring 212 can be formed to have a single-layer structure or a layered structure using a metal material such as molybdenum (Mo), titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), copper (Cu), chromium (Cr), neodymium (Nd), or scandium (Sc), or an alloy material containing any of these elements as its main component.

Since the conductive layer is formed into a wiring, it is preferable to use Al or Cu which is a low-resistance material. When Al or Cu is used, signal delay is reduced, so that higher image quality can be realized. Al has low heat resistance; therefore, defects due to a hillock, a whisker, or migration tend to be caused. In order to prevent migration of Al, a layered structure including Al and a metal material having a higher melting point than Al such as Mo, Ti, or W is preferably used. In the case where a material containing Al is used for the conductive layer, the maximum process temperature in later steps is preferably lower than or equal to 380° C., further preferably lower than or equal to 350° C.

Also when Cu is used for the conductive layer, in order to prevent a defect due to migration and diffusion of Cu elements, a layered structure including Cu and a metal material having a higher melting point than Cu, such as Mo, Ti, or W, is preferably used. Further, in the case where a material containing Cu is used for the conductive layer, the maximum process temperature in later steps is preferably lower than or equal to 450° C.

In this embodiment, as the conductive layer, a Ti layer with a thickness of 5 nm is formed over the base layer 201 and a Cu layer with a thickness of 250 nm is formed over the Ti layer. Then, the conductive layer is selectively removed by etching through the first photolithography step, whereby the gate electrode 202, the wiring 203, and the wiring 212 are formed (see FIG. 9A). The formed gate electrode 202, wiring 203, and wiring 212 preferably have tapered edges because coverage with an insulating layer or a conductive layer that is later to be stacked thereover can be improved.

Note that the resist mask used in the photolithography step may be formed by an inkjet method. An inkjet method needs no photomask; thus, manufacturing cost can be further reduced. The resist mask is to be removed after the etching step, and the description about the removal of the resist mask in each photolithography step is omitted in this embodiment. In addition, unless otherwise specified, a photolithography step in this specification includes a step of forming a resist mask, a step of etching a conductive layer or an insulating layer, and a step of removing the resist mask.

Then, the gate insulating layer 204 is formed with a thickness of greater than or equal to 50 nm and less than or equal to 800 nm, preferably greater than or equal to 100 nm and less than or equal to 600 nm over the gate electrode 202, the wiring 203, and the wiring 212. The gate insulating layer 204 can be formed using silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, tantalum oxide, gallium oxide, yttrium oxide, lanthanum oxide, hafnium oxide, hafnium silicate (HfSi_(x)O_(y) (x>0, y>0)), hafnium silicate to which nitrogen is added, hafnium aluminate to which nitrogen is added, or the like by a plasma CVD method, a sputtering method, or the like. The gate insulating layer 204 is not limited to a single layer, and a stack of different layers may be used. For example, the gate insulating layer 204 may be formed in the following manner: a silicon nitride (SiN_(y) (y>0)) layer is formed by a plasma CVD method as a gate insulating layer A and a silicon oxide (SiO_(x) (x>0)) layer is stacked over the gate insulating layer A as a gate insulating layer B.

Other than a sputtering method and a plasma CVD method, the gate insulating layer 204 can be formed by a film formation method such as a high-density plasma CVD method using microwaves (e.g., a frequency of 2.45 GHz).

In this embodiment, a stack of layers of silicon nitride and silicon oxide is used as the gate insulating layer 204. Specifically, a layer of silicon nitride is formed with a thickness of 50 nm over the gate electrode 202, and a layer of silicon oxide is formed with a thickness of 100 nm over the layer of silicon nitride.

In addition, the gate insulating layer 204 also serves as a protective layer. With a structure in which the gate electrode 202 containing Cu is covered with the insulating layer containing silicon nitride, diffusion of Cu from the gate electrode 202 can be prevented.

In the case where the semiconductor layer formed later is formed using an oxide semiconductor, the gate insulating layer 204 may be formed using an insulating material containing the same kind of component as the oxide semiconductor. In the case of stacking layers of different materials to form the gate insulating layer 204, a layer in contact with the oxide semiconductor may be formed using an insulating material containing the same kind of component as the oxide semiconductor. This is because such a material is compatible with the oxide semiconductor, and therefore, the use of such a material for the gate insulating layer 204 enables a state of the interface between the gate insulating layer 204 and the oxide semiconductor to be kept well. Here, “the same kind of component as the oxide semiconductor” means one or more elements selected from constituent elements of the oxide semiconductor. For example, in the case where the oxide semiconductor is formed using an In—Ga—Zn-based oxide semiconductor material, gallium oxide is given as an insulating material containing the same kind of component as the oxide semiconductor.

In the case of employing a layered structure for the gate insulating layer 204, the gate insulating layer 204 may have a layered structure of a film formed using an insulating material containing the same kind of component as the oxide semiconductor and a film formed using a material different from that of the film.

In order that the oxide semiconductor layer does not contain hydrogen, a hydroxyl group, and moisture as little as possible, it is preferable to preheat the substrate 200 in a preheating chamber of a sputtering apparatus as pretreatment before the formation of the oxide semiconductor layer so that impurities such as hydrogen or moisture adsorbed on the substrate 200 or the gate insulating layer 204 are eliminated and removed. As an evacuation unit provided in the preheating chamber, a cryopump is preferable. Note that this preheating treatment can be omitted. Further, this preheating may be similarly performed on the substrate 200 over which the gate electrode 202, the wiring 203, and the wiring 212 are formed before the formation of the gate insulating layer 204.

An oxide semiconductor to be used for the semiconductor layer 205 preferably contains at least indium (In) or zinc (Zn). In particular, both In and Zn are preferably contained. As a stabilizer for reducing variation in electrical characteristics of a transistor including the oxide semiconductor, gallium (Ga) is preferably additionally contained. Tin (Sn) is preferably contained as a stabilizer. Hafnium (Hf) is preferably contained as a stabilizer. Aluminum (Al) is preferably contained as a stabilizer.

As another stabilizer, one or plural kinds of lanthanoid such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu) may be contained.

As the oxide semiconductor, for example, an indium oxide, a tin oxide, a zinc oxide, a two-component metal oxide such as an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, or an In—Ga-based oxide, a three-component metal oxide such as an In—Ga—Zn-based oxide (also referred to as IGZO), an In—Al—Zn-based oxide, an In—Sn—Zn-based oxide, a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, an In—Hf—Zn-based oxide, an In—La—Zn-based oxide, an In—Ce—Zn-based oxide, an In—Pr—Zn-based oxide, an In—Nd—Zn-based oxide, an In—Sm—Zn-based oxide, an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide, an In—Tb—Zn-based oxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-based oxide, an In—Er—Zn-based oxide, an In—Tm—Zn-based oxide, an In—Yb—Zn-based oxide, or an In—Lu—Zn-based oxide, and a four-component metal oxide such as an In—Sn—Ga—Zn-based oxide, an In—Hf—Ga—Zn-based oxide, an In—Al—Ga—Zn-based oxide, an In—Sn—Al—Zn-based oxide, an In—Sn—Hf—Zn-based oxide, or an In—Hf—Al—Zn-based oxide can be used.

The oxide semiconductor layer is preferably formed using an oxide semiconductor which contains In, further preferably an oxide semiconductor which contains In and Ga. It is effective to perform dehydration or dehydrogenation in a later step in order to increase the purity of the oxide semiconductor layer.

Here, for example, an In—Ga—Zn-based oxide means an oxide containing indium (In), gallium (Ga), and zinc (Zn) and there is no particular limitation on the ratio of In:Ga:Zn. The In—Ga—Zn-based oxide may contain a metal element other than In, Ga, and Zn.

For the oxide semiconductor layer, a thin film expressed by a chemical formula InMO₃(ZnO)_(m) (m>0) can be used. Here, M represents one or more metal elements selected from Sn, Zn, Ga, Al, Mn, and Co. As the oxide semiconductor, a material expressed by In₃SnO₅(ZnO)_(n) (n>0) may also be used.

For example, an In—Ga—Zn-based oxide with an atomic ratio of In:Ga:Zn=1:1:1 (=1/3:1/3:1/3) or In:Ga:Zn=2:2:1 (=2/5:2/5:1/5), or any of oxides whose composition is in the neighborhood of the above compositions can be used. Alternatively, an In—Sn—Zn-based oxide with an atomic ratio of In:Sn:Zn=1:1:1 (=1/3:1/3:1/3), In:Sn:Zn=2:1:3 (=1/3:1/6:1/2), or In:Sn:Zn=2:1:5 (=1/4:1/8:5/8), or any of oxides whose composition is in the neighborhood of the above compositions may be used.

However, the composition is not limited to those described above, and a material having an appropriate composition may be used depending on necessary semiconductor characteristics (e.g., mobility, threshold voltage, and variation). In order to obtain necessary semiconductor characteristics, it is preferable that the carrier concentration, the impurity concentration, the defect density, the atomic ratio of a metal element to oxygen, the interatomic distance, the density, and the like be set to be appropriate.

For example, with the In—Sn—Zn-based oxide, a high mobility can be relatively easily obtained. However, the mobility can be increased by reducing the defect density in the bulk also in the case of using the In—Ga—Zn-based oxide.

Note that for example, the expression “the composition of an oxide including In, Ga, and Zn at the atomic ratio, In:Ga:Zn=a:b:c (a+b+c=1), is in the neighborhood of the composition of an oxide including In, Ga, and Zn at the atomic ratio, In:Ga:Zn=A:B:C (A+B+C=1)” means that a, b, and c satisfy the following relation: (a−A)²+(b−B)²+(c−C)²≦r², and r may be 0.05, for example. The same applies to other oxides.

The oxide semiconductor may be either single crystal or non-single-crystal. In the latter case, the oxide semiconductor may be either amorphous or polycrystal. Further, the oxide semiconductor may have either an amorphous structure including a portion having crystallinity or a non-amorphous structure.

In an oxide semiconductor in an amorphous state, a flat surface can be obtained relatively easily, so that when a transistor is manufactured with the use of the oxide semiconductor, interface scattering can be reduced, and relatively high mobility can be obtained relatively easily.

In an oxide semiconductor having crystallinity, defects in the bulk can be further reduced and when a surface flatness is improved, a mobility higher than that of an oxide semiconductor in an amorphous state can be obtained. In order to improve the surface flatness, the oxide semiconductor is preferably formed over a flat surface. Specifically, the oxide semiconductor may be formed over a surface with the average surface roughness (R_(a)) of less than or equal to 1 nm, preferably less than or equal to 0.3 nm, further preferably less than or equal to 0.1 nm. R_(a) can be measured using an atomic force microscope (AFM).

As the oxide semiconductor having crystallinity, an oxide including a crystal with c-axis alignment (also referred to as C-Axis Aligned Crystal (CAAC)), which has a triangular or hexagonal atomic arrangement when seen from the direction of an a-b plane, a surface, or an interface may be used. In the crystal, metal atoms are arranged in a layered manner, or metal atoms and oxygen atoms are arranged in a layered manner along the c-axis, and the direction of the a-axis or the b-axis is varied in the a-b plane (the crystal rotates around the c-axis).

In a broad sense, an oxide including CAAC means a non-single-crystal oxide including a phase which has a triangular, hexagonal, regular triangular, or regular hexagonal atomic arrangement when seen from the direction perpendicular to the a-b plane and in which metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis direction.

The CAAC is not a single crystal, but this does not mean that the CAAC is composed of only an amorphous component. Although the CAAC includes a crystallized portion (crystalline portion), a boundary between one crystalline portion and another crystalline portion is not clear in some cases.

In the case where oxygen is included in the CAAC, nitrogen may be substituted for part of oxygen included in the CAAC. The c-axes of individual crystalline portions included in the CAAC may be aligned in one direction (e.g., a direction perpendicular to a surface of a substrate over which the CAAC is formed or a surface of the CAAC). Alternatively, the normals of the a-b planes of the individual crystalline portions included in the CAAC may be aligned in one direction (e.g., a direction perpendicular to a surface of a substrate over which the CAAC is formed or a surface of the CAAC).

The CAAC becomes a conductor, a semiconductor, or an insulator depending on its composition or the like. The CAAC transmits or does not transmit visible light depending on its composition or the like.

As an example of such a CAAC, there is a crystal which is formed into a film shape and has a triangular or hexagonal atomic arrangement when observed from the direction perpendicular to a surface of the film or a surface of a supporting substrate, and in which metal atoms are arranged in a layered manner or metal atoms and oxygen atoms (or nitrogen atoms) are arranged in a layered manner when a cross section of the film is observed.

An example of a crystal structure of the CAAC will be described in detail with reference to FIGS. 15A to 15E, FIGS. 16A to 16C, and FIGS. 17A to 17C. In FIGS. 15A to 15E, FIGS. 16A to 16C, and FIGS. 17A to 17C, the vertical direction corresponds to the c-axis direction and a plane perpendicular to the c-axis direction corresponds to the a-b plane, unless otherwise specified. When the expressions “an upper half” and “a lower half” are simply used, they refer to an upper half above the a-b plane and a lower half below the a-b plane (an upper half and a lower half with respect to the a-b plane). Furthermore, in FIGS. 15A to 15E, 0 surrounded by a circle represents tetracoodianate O and a double circle represents tricoodenate O.

FIG. 15A illustrates a structure including one hexacoordinate In atom and six tetracoordinate oxygen (hereinafter referred to as tetracoordinate O) atoms proximate to the In atom. Here, a structure including one metal atom and oxygen atoms proximate thereto is referred to as a small group. The structure in FIG. 15A is actually an octahedral structure, but is illustrated as a planar structure for simplicity. Note that three tetracoordinate O atoms exist in each of an upper half and a lower half in FIG. 15A. In the small group illustrated in FIG. 15A, electric charge is 0.

FIG. 15B illustrates a structure including one pentacoordinate Ga atom, three tricoordinate oxygen (hereinafter referred to as tricoordinate O) atoms proximate to the Ga atom, and two tetracoordinate O atoms proximate to the Ga atom. All the tricoordinate O atoms exist on the a-b plane. One tetracoordinate O atom exists in each of an upper half and a lower half in FIG. 15B. An In atom can also have the structure illustrated in FIG. 15B because an In atom can have five ligands. In the small group illustrated in FIG. 15B, electric charge is 0.

FIG. 15C illustrates a structure including one tetracoordinate Zn atom and four tetracoordinate O atoms proximate to the Zn atom. In FIG. 15C, one tetracoordinate O atom exists in an upper half and three tetracoordinate O atoms exist in a lower half. Alternatively, three tetracoordinate O atoms may exist in the upper half and one tetracoordinate O atom may exist in the lower half in FIG. 15C. In the small group illustrated in FIG. 15C, electric charge is 0.

FIG. 15D illustrates a structure including one hexacoordinate Sn atom and six tetracoordinate O atoms proximate to the Sn atom. In FIG. 15D, three tetracoordinate O atoms exist in each of an upper half and a lower half. In the small group illustrated in FIG. 15D, electric charge is +1.

FIG. 15E illustrates a small group including two Zn atoms. In FIG. 15E, one tetracoordinate O atom exists in each of an upper half and a lower half. In the small group illustrated in FIG. 15E, electric charge is −1.

Here, a plurality of small groups form a medium group, and a plurality of medium groups form a large group (also referred to as a unit cell).

Now, a rule of bonding between the small groups will be described. The three O atoms in the upper half with respect to the hexacoordinate In atom in FIG. 15A each have three proximate In atoms in the downward direction, and the three O atoms in the lower half each have three proximate In atoms in the upward direction. The one O atom in the upper half with respect to the pentacoordinate Ga atom in FIG. 15B has one proximate Ga atom in the downward direction, and the one O atom in the lower half has one proximate Ga atom in the upward direction. The one O atom in the upper half with respect to the tetracoordinate Zn atom in FIG. 15C has one proximate Zn atom in the downward direction, and the three O atoms in the lower half each have three proximate Zn atoms in the upward direction. In this manner, the number of the tetracoordinate O atoms above the metal atom is equal to the number of the metal atoms proximate to and below each of the tetracoordinate O atoms. Similarly, the number of the tetracoordinate O atoms below the metal atom is equal to the number of the metal atoms proximate to and above each of the tetracoordinate O atoms. Since the coordination number of the tetracoordinate O atom is 4, the sum of the number of the metal atoms proximate to and below the O atom and the number of the metal atoms proximate to and above the O atom is 4. Accordingly, when the sum of the number of tetracoordinate O atoms above a metal atom and the number of tetracoordinate O atoms below another metal atom is 4, the two kinds of small groups including the metal atoms can be bonded. For example, in the case where the hexacoordinate metal (In or Sn) atom is bonded through three tetracoordinate O atoms in the lower half, it is bonded to the pentacoordinate metal (Ga or In) atom or the tetracoordinate metal (Zn) atom.

A metal atom whose coordination number is 4, 5, or 6 is bonded to another metal atom through a tetracoordinate O atom in the c-axis direction. In addition to the above, a medium group can be formed in a different manner by combining a plurality of small groups so that the total electric charge of the layered structure is 0.

FIG. 16A illustrates a model of a medium group included in a layered structure of an In—Sn—Zn-based oxide. FIG. 16B illustrates a large group including three medium groups. Note that FIG. 16C illustrates an atomic arrangement in the case where the layered structure in FIG. 16B is observed from the c-axis direction.

In FIG. 16A, a tricoordinate O atom is omitted for simplicity, and a tetracoordinate O atom is illustrated by a circle; the number in the circle shows the number of tetracoordinate O atoms. For example, three tetracoordinate O atoms existing in each of an upper half and a lower half with respect to a Sn atom are denoted by circled 3. Similarly, in FIG. 16A, one tetracoordinate O atom existing in each of an upper half and a lower half with respect to an In atom is denoted by circled 1. FIG. 16A also illustrates a Zn atom proximate to one tetracoordinate O atom in a lower half and three tetracoordinate O atoms in an upper half, and a Zn atom proximate to one tetracoordinate O atom in an upper half and three tetracoordinate O atoms in a lower half.

In the medium group included in the layered structure of the In—Sn—Zn-based oxide in FIG. 16A, in the order starting from the top, a Sn atom proximate to three tetracoordinate O atoms in each of an upper half and a lower half is bonded to an In atom proximate to one tetracoordinate O atom in each of an upper half and a lower half, the In atom is bonded to a Zn atom proximate to three tetracoordinate O atoms in an upper half, the Zn atom is bonded to an In atom proximate to three tetracoordinate O atoms in each of an upper half and a lower half through one tetracoordinate O atom in a lower half with respect to the Zn atom, the In atom is bonded to a small group that includes two Zn atoms and is proximate to one tetracoordinate O atom in an upper half, and the small group is bonded to a Sn atom proximate to three tetracoordinate O atoms in each of an upper half and a lower half through one tetracoordinate O atom in a lower half with respect to the small group. A plurality of such medium groups are bonded, so that a large group is formed.

Here, electric charge for one bond of a tricoordinate O atom and electric charge for one bond of a tetracoordinate O atom can be assumed to be −0.667 and −0.5, respectively. For example, electric charge of a (hexacoordinate or pentacoordinate) In atom, electric charge of a (tetracoordinate) Zn atom, and electric charge of a (pentacoordinate or hexacoordinate) Sn atom are +3, +2, and +4, respectively. Accordingly, electric charge in a small group including a Sn atom is +1. Therefore, electric charge of −1, which cancels+1, is needed to form a layered structure including a Sn atom. As a structure having electric charge of −1, the small group including two Zn atoms as illustrated in FIG. 15E can be given. For example, with one small group including two Zn atoms, electric charge of one small group including a Sn atom can be cancelled, so that the total electric charge of the layered structure can be 0.

When the large group illustrated in FIG. 16B is repeated, an In—Sn—Zn-based oxide crystal (In₂SnZn₃O₈) can be obtained. Note that a layered structure of the obtained In—Sn—Zn-based oxide can be expressed as a composition formula, In₂SnZn₂O₇(ZnO)_(m) (m is 0 or a natural number).

The above-described rule also applies to the following oxides: a four-component metal oxide such as an In—Sn—Ga—Zn-based oxide; a three-component metal oxide such as an In—Ga—Zn-based oxide (also referred to as IGZO), an In—Al—Zn-based oxide, a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, an In—Hf—Zn-based oxide, an In—La—Zn-based oxide, an In—Ce—Zn-based oxide, an In—Pr—Zn-based oxide, an In—Nd—Zn-based oxide, an In—Sm—Zn-based oxide, an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide, an In—Tb—Zn-based oxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-based oxide, an In—Er—Zn-based oxide, an In—Tm—Zn-based oxide, an In—Yb—Zn-based oxide, or an In—Lu—Zn-based oxide; a two-component metal oxide such as an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, or an In—Ga-based oxide; and the like.

As an example, FIG. 17A illustrates a model of a medium group included in a layered structure of an In—Ga—Zn-based oxide.

In the medium group included in the layered structure of the In—Ga—Zn-based oxide in FIG. 17A, in the order starting from the top, an In atom proximate to three tetracoordinate O atoms in each of an upper half and a lower half is bonded to a Zn atom proximate to one tetracoordinate O atom in an upper half, the Zn atom is bonded to a Ga atom proximate to one tetracoordinate O atom in each of an upper half and a lower half through three tetracoordinate O atoms in a lower half with respect to the Zn atom, and the Ga atom is bonded to an In atom proximate to three tetracoordinate O atoms in each of an upper half and a lower half through one tetracoordinate O atom in a lower half with respect to the Ga atom. A plurality of such medium groups are bonded, so that a large group is formed.

FIG. 17B illustrates a large group including three medium groups. Note that FIG. 17C illustrates an atomic arrangement in the case where the layered structure in FIG. 17B is observed from the c-axis direction.

Here, since electric charge of a (hexacoordinate or pentacoordinate) In atom, electric charge of a (tetracoordinate) Zn atom, and electric charge of a (pentacoordinate) Ga atom are +3, +2, and +3, respectively, electric charge of a small group including any of an In atom, a Zn atom, and a Ga atom is 0. As a result, the total electric charge of a medium group having a combination of such small groups is always 0.

In order to form the layered structure of the In—Ga—Zn-based oxide, a large group can be formed using not only the medium group illustrated in FIG. 17A but also a medium group in which the arrangement of the In atom, the Ga atom, and the Zn atom is different from that in FIG. 17A.

When the large group illustrated in FIG. 17B is repeated, a crystal of an In—Ga—Zn-based oxide can be obtained. Note that a layered structure of the obtained In—Ga—Zn-based oxide can be expressed as a composition formula, InGaO₃(ZnO)_(n) (n is a natural number).

In the case where n=1 (InGaZnO₄), a crystal structure illustrated in FIG. 18A can be obtained, for example. Note that in the crystal structure in FIG. 18A, since a Ga atom and an In atom each have five ligands as illustrated in FIG. 15B, a structure in which Ga is replaced with In can be obtained.

In the case where n=2 (InGaZn₂O₅), a crystal structure illustrated in FIG. 18B can be obtained, for example. Note that in the crystal structure in FIG. 18B, since a Ga atom and an In atom each have five ligands as described in FIG. 15B, a structure in which Ga is replaced with In can be obtained.

Then, the oxide semiconductor layer 205 is formed by a sputtering method, an evaporation method, a PCVD method, a PLD method, an ALD method, an MBE method, or the like.

The oxide semiconductor layer 205 is formed in an oxygen gas atmosphere preferably by a sputtering method. At this time, the substrate temperature is set to higher than or equal to 100° C. and lower than or equal to 600° C., preferably higher than or equal to 150° C. and lower than or equal to 550° C., further preferably higher than or equal to 200° C. and lower than or equal to 500° C. The thickness of the oxide semiconductor layer 205 is greater than or equal to 1 nm and less than or equal to 40 nm, preferably greater than or equal to 3 nm and less than or equal to 20 nm. As the substrate temperature in film formation is higher, the impurity concentration in the obtained oxide semiconductor layer 205 is lower. Further, the atomic arrangement in the oxide semiconductor layer 205 is ordered, the density thereof is increased, so that a polycrystal or a CAAC is likely to be formed. Furthermore, since an oxygen gas atmosphere is employed for the film formation, an unnecessary atom such as a rare gas atom is not contained in the oxide semiconductor layer 205, so that a polycrystal or a CAAC is likely to be formed. Note that a mixed gas atmosphere including an oxygen gas and a rare gas may be used. In that case, the percentage of an oxygen gas is higher than or equal to 30 vol. %, preferably higher than or equal to 50 vol. %, further preferably higher than or equal to 80 vol. %. Note that as the oxide semiconductor layer 205 is thinner, a short-channel effect of a transistor is reduced. However, when the oxide semiconductor layer 205 is too thin, influence of interface scattering is enhanced; thus, the field effect mobility might be decreased (see FIG. 9B).

In the case of forming the oxide semiconductor layer 205 using an In—Ga—Zn-based oxide material by a sputtering method, it is preferable to use an In—Ga—Zn-based oxide target having an atomic ratio of In:Ga:Zn=1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3, or 3:1:4. When the oxide semiconductor layer 205 is formed using an In—Ga—Zn-based oxide target having the aforementioned atomic ratio, a polycrystal or a CAAC is likely to be formed. Note that an In—Ga—Zn-based oxide semiconductor can be referred to as IGZO.

An In—Sn—Zn-based oxide semiconductor can be referred to as ITZO. In the case of fanning the oxide semiconductor layer 205 using an In—Sn—Zn-based oxide material by a sputtering method, it is preferable to use an In—Sn—Zn-based oxide target having an atomic ratio of In:Sn:Zn=1:1:1, 2:1:3, 1:2:2, or 20:45:35. When the oxide semiconductor layer 205 is formed using an In—Sn—Zn-based oxide target having the aforementioned atomic ratio, a polycrystal or a CAAC is likely to be formed.

In this embodiment, the oxide semiconductor layer with a thickness of 30 nm is formed by a sputtering method with the use of an In—Ga—Zn-based oxide target. The oxide semiconductor layer can be fainted by a sputtering method in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen (see FIG. 9B).

As a target used for forming the oxide semiconductor layer by a sputtering method, for example, a metal oxide target having the following composition ratio is used: In₂O₃:Ga₂O₃:ZnO is 1:1:1 [molar ratio]; thus, an In—Ga—Zn—O layer is formed. Without limitation to the material and the composition of this target, for example, a metal oxide target containing In₂O₃, Ga₂O₃, and ZnO at 1:1:2 [molar ratio] may be used.

The relative density of the metal oxide target is higher than or equal to 90% and lower than or equal to 100%, preferably higher than or equal to 95% and lower than or equal to 99.9%. With the use of a metal oxide target with a high relative density, the formed oxide semiconductor layer can be dense.

It is preferable that a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or hydride are removed be used as a sputtering gas for the formation of the oxide semiconductor layer. For example, in the case where argon is used for the sputtering gas, it is preferable that the purity be 9N, the dew point be −121° C., the content of H₂O be lower than or equal to 0.1 ppb, and the content of H₂ be lower than or equal to 0.5 ppb. In the case where oxygen is used for the sputtering gas, it is preferable that the purity be 8N, the dew point be −112° C., the content of H₂O be lower than or equal to 1 ppb, and the content of H₂ be lower than or equal to 1 ppb.

When the oxide semiconductor layer is formed, the substrate is held in a film formation chamber kept under a reduced pressure, and the substrate temperature is set to a temperature of higher than or equal to 100° C. and lower than or equal to 600° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C. Note that in the case where Al is used for the wiring layer formed through the first photolithography step, the substrate temperature is set to lower than or equal to 380° C., preferably lower than or equal to 350° C. Alternatively, in the case where Cu is used for the wiring layer formed through the first photolithography step, the substrate temperature is set to lower than or equal to 450° C.

By heating the substrate during the film formation, the concentration of impurities such as hydrogen, moisture, hydride, or hydroxide in the oxide semiconductor layer can be reduced. In addition, damage by sputtering can be reduced. Then, a sputtering gas from which hydrogen and moisture are removed is introduced into the film formation chamber and moisture remaining therein is removed, and the oxide semiconductor layer is formed with the use of the above target.

In order to remove moisture remaining in the film formation chamber, an entrapment vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump is preferably used. As an evacuation unit, a turbo molecular pump provided with a cold trap may be used. In the film formation chamber which is evacuated with the cryopump, a hydrogen atom, a compound containing a hydrogen atom such as water (H₂O) (more preferably, also a compound containing a carbon atom), and the like are removed, whereby the impurity concentration in the oxide semiconductor layer formed in the film formation chamber can be reduced.

An example of the film formation conditions is as follows: the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, the electric power of the DC power source is 0.5 kW, and oxygen (the flow rate of oxygen is 100%) is used as a sputtering gas. Note that a pulsed direct-current power source is preferably used, in which case powder substances (also referred to as particles or dust) that are generated in film formation can be reduced and the film thickness can be uniform.

The concentrations of alkali metals such as sodium (Na), lithium (Li), and potassium (K) in the oxide semiconductor layer are as follows. The concentration of Na is lower than or equal to 5×10¹⁶ cm⁻³, preferably lower than or equal to 1×10¹⁶ cm⁻³, further preferably lower than or equal to 1×10¹⁵ cm³. The concentration of Li is lower than or equal to 5×10¹⁵ cm³, preferably lower than or equal to 1×10¹⁵ cm⁻³. The concentration of K is lower than or equal to 5×10¹⁵ cm⁻³, preferably lower than or equal to 1×10¹⁵ cm⁻³.

It has been pointed out that an oxide semiconductor is insensitive to impurities, there is no problem when a considerable amount of metal impurities is contained in the oxide semiconductor, and therefore, soda-lime glass which contains a large amount of alkali metal such as sodium and is inexpensive can also be used (Kamiya, Nomura, and Hosono, “Carrier Transport Properties and Electronic Structures of Amorphous Oxide Semiconductors: The present status”, KOTAI BUTSURI (SOLID STATE PHYSICS), 2009, Vol. 44, pp. 621-633). However, this is not a proper consideration. Alkali metal is not an element for forming in an oxide semiconductor, and therefore, is an impurity. Also, alkaline-earth metal is an impurity in the case where alkaline-earth metal is not an element for forming an oxide semiconductor. Alkali metal, in particular, Na becomes Na⁺ when an insulating layer in contact with the oxide semiconductor layer is an oxide and Na diffuses into the insulating layer. Further, in the oxide semiconductor layer, Na cuts or enters a bond between metal and oxygen which are included in the oxide semiconductor. As a result, for example, deterioration of characteristics of the transistor, such as a normally-on state of the transistor due to shift of a threshold voltage in the negative direction, or reduction in mobility, occurs. In addition, variation in characteristics also occurs. Such deterioration of characteristics of the transistor and variation in characteristics due to the impurity remarkably appear when the hydrogen concentration in the oxide semiconductor layer is very low. Therefore, the concentrations of alkali metals in the oxide semiconductor is strongly required to set in the aforementioned ranges in the case where the hydrogen concentration in the oxide semiconductor is lower than or equal to 5×10¹⁹ cm⁻³, particularly lower than or equal to 5×10¹⁸ cm⁻³.

Next, first heat treatment is performed. By the first heat treatment, excessive hydrogen (including water and a hydroxyl group) in the oxide semiconductor layer is removed (dehydration or dehydrogenation), whereby the impurity concentration in the oxide semiconductor layer can be reduced.

The first heat treatment is preferably performed at a temperature of higher than or equal to 250° C. and lower than or equal to 750° C., or higher than or equal to 400° C. and lower than the strain point of the substrate in a reduced pressure atmosphere, an inert gas atmosphere such as a nitrogen atmosphere or a rare gas atmosphere, an oxygen gas atmosphere, or an ultra dry air atmosphere (in air whose moisture content is lower than or equal to 20 ppm (the dew point: −55° C.), preferably lower than or equal to 1 ppm, further preferably lower than or equal to 10 ppb in the case where measurement is performed using a dew-point meter of a cavity ring-down laser spectroscopy (CRDS) system). Note that in the case where Al is used for the wiring layer formed through the first photolithography step, the heat treatment temperature is set to lower than or equal to 380° C., preferably lower than or equal to 350° C. Alternatively, in the case where Cu is used for the wiring layer formed through the first photolithography step, the heat treatment temperature is set to lower than or equal to 450° C. In this embodiment, the substrate is introduced into an electric furnace which is a kind of heat treatment apparatuses, and heat treatment is performed on the oxide semiconductor layer at 450° C. in a nitrogen atmosphere for one hour.

Note that the heat treatment apparatus is not limited to the electrical furnace, and may include a device for heating a process object by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (rapid thermal anneal) apparatus such as a GRTA (gas rapid thermal anneal) apparatus or an LRTA (lamp rapid thermal anneal) apparatus can be used. An LRTA apparatus is an apparatus for heating a process object by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. A GRTA apparatus is an apparatus for heat treatment using a high-temperature gas. As the high-temperature gas, an inert gas which does not react with a process object by heat treatment, such as nitrogen or a rare gas such as argon, is used.

For example, as the first heat treatment, GRTA may be performed as follows. The substrate is transferred and put in an inert gas heated to a high temperature, is heated for several minutes, and is transferred and taken out of the inert gas heated to the high temperature.

When the heat treatment is performed in an atmosphere of an inert gas such as nitrogen or a rare gas, oxygen, or ultra-dry air, it is preferable that the atmosphere do not contain water, hydrogen, or the like. It is also preferable that the purity of nitrogen, oxygen, or the rare gas which is introduced into a heat treatment apparatus be set to be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower).

The first heat treatment is preferably performed in such a manner that after heat treatment is performed in a reduced pressure atmosphere or an inert atmosphere, the atmosphere is switched to an oxidation atmosphere with the temperature maintained and heat treatment is further performed. When the heat treatment is performed in a reduced pressure atmosphere or an inert atmosphere, the impurity concentration in the oxide semiconductor layer can be reduced; however, oxygen vacancies are caused at the same time. By the heat treatment in the oxidation atmosphere, the caused oxygen vacancies can be reduced.

The carrier concentration of the oxide semiconductor, in which hydrogen is reduced to a sufficiently low concentration so that the oxide semiconductor is purified and in which defect states in an energy gap due to oxygen deficiency are reduced by sufficiently supplying oxygen, is lower than 1×10¹²/cm³, preferably lower than 1×10¹¹/cm³, further preferably lower than 1.45×10¹⁰/cm³. For example, the off-state current (per unit channel width (1 μm) here) at room temperature (25° C.) is 100 zA (1 zA (zeptoampere) is 1×10⁻²¹ A) or less, preferably 10 zA or less. The off-state current at 85° C. is 100 zA (1×10⁻¹⁹ A) or less, preferably 10 zA (1×10⁻²⁰ A) or less. The transistor 111 with very excellent off-state current characteristics can be obtained with the use of such an i-type (intrinsic) or substantially i-type oxide semiconductor.

The electrical characteristics of a transistor including a purified oxide semiconductor, such as the threshold voltage and the on-state current, have almost no temperature dependence. Further, transistor characteristics hardly change due to light deterioration.

As described above, variation in electric characteristics of a transistor including a purified and electrically i-type (intrinsic) oxide semiconductor obtained by reducing the oxygen deficiency is suppressed and thus, the transistor is electrically stable. Accordingly, a liquid crystal display device including an oxide semiconductor, which has high reliability and stable electric characteristics, can be provided.

Next, a conductive layer to be processed into the source electrode 206 a, the drain electrode 206 b, and the wiring 216 is formed over the semiconductor layer 205. The conductive layer for forming the source electrode 206 a, the drain electrode 206 b, and the wiring 216 can be formed using a material and a method similar to those of the gate electrode 202. The conductive layer for forming the source electrode 206 a, the drain electrode 206 b, and the wiring 216 may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In₂O₃), tin oxide (SnO₂), zinc oxide (ZnO), indium oxide-tin oxide alloy (In₂O₃—SnO₂; abbreviated to ITO), indium oxide-zinc oxide alloy (In₂O₃—ZnO), or any of these metal oxide materials in which silicon or silicon oxide is contained can be used.

In this embodiment, the conductive layer is formed as follows: a Ti layer with a thickness of 5 nm is formed over the semiconductor layer 205, and a Cu layer with a thickness of 250 nm is formed over the Ti layer. Then, a resist mask is formed by a second photolithography step and the conductive layer is selectively etched; thus, the source electrode 206 a, the drain electrode 206 b, and the wiring 216 are formed (see FIG. 9C).

Next, the insulating layer 207 is formed over the source electrode 206 a, the drain electrode 206 b, and the wiring 216 (see FIG. 10A). The insulating layer 207 can be formed using a material and a method similar to those of the gate insulating layer 204 or the base layer 201. Sputtering is preferably employed in terms of low possibility of entry of hydrogen, water, and the like. If hydrogen is contained in the insulating layer 207, hydrogen might enter the oxide semiconductor layer or extract oxygen in the oxide semiconductor layer, which might cause a reduction in resistance of the oxide semiconductor layer (which means that the oxide semiconductor layer becomes n-type). Therefore, it is important to use a method by which hydrogen and an impurity containing hydrogen are not mixed in the insulating layer 207, for forming the insulating layer 207.

As the insulating layer 207, an inorganic insulating material such as silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, or gallium oxide can be typically used. Gallium oxide is a material which is hardly charged; therefore, variation in threshold voltage due to charge buildup of the insulating layer can be suppressed. Note that in the case where an oxide semiconductor is used for the semiconductor layer 205, a metal oxide layer containing the same kind of component as the oxide semiconductor may be formed as the insulating layer 207 or stacked over the insulating layer 207.

In this embodiment, a 200-nm-thick silicon oxide layer is formed as the insulating layer 207 by a sputtering method. The substrate temperature in film formation may be higher than or equal to room temperature and lower than or equal to 300° C. and in this embodiment, is 100° C. The silicon oxide layer can be formed by sputtering in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen. As a target, a silicon oxide target or a silicon target can be used. For example, a silicon oxide layer can be formed by sputtering in an atmosphere containing oxygen with the use of silicon for the target.

In order to remove remaining moisture from the deposition chamber at the time of formation of the insulating layer 207, an entrapment vacuum pump (e.g., a cryopump) is preferably used. When the insulating layer 207 is formed in the deposition chamber evacuated using a cryopump, the impurity concentration in the insulating layer 207 can be reduced. In addition, as an exhaustion unit for removing moisture remaining in the chamber used for depositing the insulating layer 207, a turbo molecular pump provided with a cold trap may be used.

It is preferable that a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or a hydride have been removed be used as a sputtering gas for the formation of the insulating layer 207.

Then, second heat treatment may be performed in a reduced pressure atmosphere, an inert gas atmosphere, an oxygen gas atmosphere, or an ultra-dry air atmosphere (preferably at higher than or equal to 200° C. and lower than or equal to 600° C., for example, higher than or equal to 250° C. and lower than or equal to 550° C.). Note that in the case where Al is used for a wiring layer formed by the first photolithography step or the second photolithography step, the heat treatment temperature is set to be 380° C. or lower, preferably 350° C. or lower. In the case where Cu is used for a wiring layer formed by the first photolithography step or the second photolithography step, the heat treatment temperature is set to be 450° C. or lower. For example, the second heat treatment may be performed at 450° C. for one hour in a nitrogen atmosphere. By the second heat treatment, part of the oxide semiconductor layer (a channel formation region) is heated in the state of being in contact with the insulating layer 207, so that oxygen can be supplied from the insulating layer 207 containing oxygen to the semiconductor layer 205. It is preferable that the above atmosphere do not contain water, hydrogen, or the like.

Next, a resist mask is formed by a third photolithography step, and part of the insulating layer 207 over the drain electrode 206 b is selectively removed, so that the contact hole 208 is formed. In addition, part of the insulating layer 207 over the wiring 216 in the cross section K1-K2 is selectively removed, so that the contact hole 220 is formed. Over the wiring 212 in the cross section J1-J2, part of the insulating layer 207, part of the semiconductor layer 205, and part of the gate insulating layer 204 are selectively removed, so that the contact hole 219 is formed (see FIG. 10B). Although not illustrated, by this photolithography step, the groove portions 230 are formed in a manner similar to that of the contact hole 219. Therefore, at the side surface of the groove portions 230, the insulating layer 207, the semiconductor layer 205, and the gate insulating layer 204 are exposed.

For the etching of the insulating layer 207, the semiconductor layer 205, and the gate insulating layer 204, either dry etching or wet etching or both of them may be used. For example, a gas containing chlorine (a chlorine-based gas such as chlorine (Cl₂), boron trichloride (BCl₃), silicon tetrachloride (SiCl₄), or carbon tetrachloride (CCl₄)) can be employed as an etching gas used for the dry etching.

As the dry etching, a parallel-plate reactive ion etching (RIE) method, an inductively coupled plasma (ICP) etching method, or the like can be used. Since the base layer 201 has a function of preventing diffusion of an impurity element from the substrate 200, for the above etching, etching conditions are preferably adjusted so as to etch the base layer 201 as little as possible.

In general, etching of the semiconductor layer and formation of the contact hole are separately performed through their respective photolithography steps and etching steps; according to the manufacturing process of this embodiment, etching of the semiconductor layer and formation of the contact hole can be performed by one photolithography step and one etching step. Therefore, not only the number of photomasks but the number of photolithography steps can be reduced, which can reduce the number of etching steps after the photolithography steps. That is, a liquid crystal display device can be manufactured with a small number of photolithography steps, at low cost with high productivity.

In addition, according to the manufacturing process of this embodiment, a photoresist is not directly formed on the oxide semiconductor layer. Further, since the channel formation region in the oxide semiconductor layer is protected by the insulating layer 207, moisture is not attached to the channel formation region in the oxide semiconductor layer in later separation and cleaning steps of the photoresist; thus, variation in characteristics of the transistor 111 is reduced and the reliability is increased.

Next, a light-transmitting conductive layer (also referred to as a transparent conductive layer) that is to be processed into the pixel electrode 210, the electrode 221, and the electrode 222 is formed with a thickness of more than or equal to 30 nm and less than or equal to 200 nm, preferably more than or equal to 50 nm and less than or equal to 100 nm, over the insulating layer 207 by a sputtering method, a vacuum evaporation method, or the like (see FIG. 10C).

For the light-transmitting conductive layer, a light-transmitting conductive material such as indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used. Alternatively, a material formed of one to ten graphene sheets may be used.

In this embodiment, an example of a manufacturing method of a pixel portion of a transmissive liquid crystal display device has been described. However, without limitation thereto, an embodiment of present invention can be applied to a pixel portion of a reflective or semi-transmissive liquid crystal display device as well. In the case of obtaining a pixel portion of a reflective liquid crystal display device, the pixel electrode may be formed using a conductive layer with high light reflectance (also referred to as a reflective conductive layer), for example, using a metal having high visible-light reflectance, such as aluminum, titanium, silver, rhodium, or nickel; an alloy containing at least one of the above metals; or stacked layers of the above materials. In the case of obtaining a pixel portion of a semi-transmissive liquid crystal display device, one pixel electrode is formed using a transparent conductive layer and a reflective conductive layer and provided with a transmissive portion and a reflective portion.

In this embodiment, an ITO layer with a thickness of 80 nm is formed as the light-transmitting conductive layer. By a fourth photolithography step, a resist mask is formed, and the light-transmitting conductive layer is selectively etched; thus, the pixel electrode 210, the electrode 221, and the electrode 222 are formed.

The pixel electrode 210 is electrically connected to the drain electrode 206 b through the contact hole 208. The electrode 221 is electrically connected to the wiring 212 through the contact hole 219. Further, the electrode 222 is electrically connected to the wiring 216 through the contact hole 220.

In addition, in the contact hole 219 and the contact hole 220 formed in the terminal portion 103 and the terminal portion 104, it is important that the wiring 212 and the wiring 216 be not kept in an exposed state and be covered with an oxide conductive material such as ITO. When the wiring 212 and the wiring 216 which are metal layers are kept in an exposed state, exposed surfaces are oxidized and contact resistance with an FPC or the like is increased. The increase in contact resistance causes distortion in waveform or delay of a signal that is input from the outside, and a signal from the outside cannot be transmitted correctly, so that the reliability of the semiconductor device is lowered. By covering the exposed surfaces of the wiring 212 and the wiring 216 with an oxide conductive material such as ITO, the increase in contact resistance can be prevented, and the reliability of the semiconductor device can be improved.

According to this embodiment, a semiconductor device can be manufactured through a smaller number of photolithography steps than the conventional one. Therefore, a liquid crystal display device can be manufactured at low cost with high productivity.

In this embodiment, an example of a bottom-gate transistor is described, but this embodiment can also be applied to a top-gate transistor.

This embodiment can be freely combined with any of the other embodiments.

Embodiment 2

In this embodiment, an example of a process which is partially different from that described in Embodiment 1 will be described with reference to FIGS. 11A to 11C. Note that in FIGS. 11A to 11C, the same reference numerals are used for the same parts as those in Embodiment 1, and description of the parts with the same reference numerals will be omitted here.

First, in a manner similar to that of Embodiment 1, a conductive layer is formed over a substrate 200 having an insulating surface, and then, a gate electrode 202 is formed through a first photolithography step and an etching step.

An insulating layer serving as a base layer may be provided between the substrate 200 and the gate electrode 202. In this embodiment, a base layer 201 is provided. The base layer 201 has a function of preventing diffusion of impurity elements (such as Na) from the substrate 200, and can be formed using a film selected from a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a hafnium oxide film, an aluminum oxide film, a gallium oxide film, and a gallium aluminum oxide film. The structure of the base layer is not limited to a single-layer structure, and may be a layered structure of a plurality of the above films.

In this embodiment, because the film formation temperature of a semiconductor layer to be formed later is higher than or equal to 200° C. and lower than or equal to 450° C. and the temperature of heat treatment after the formation of the semiconductor layer is higher than or equal to 200° C. and lower than or equal to 450° C., the gate electrode 202 is formed of stacked layers of copper for a lower layer and molybdenum for an upper layer or stacked layers of copper for a lower layer and tungsten for an upper layer.

Then, a gate insulating layer 204 is formed over the gate electrode 202 by a CVD method, a sputtering method, or the like in a manner similar to that of Embodiment 1. The structure obtained through the process up to here is illustrated in the cross-sectional view of FIG. 11A.

Next, a first oxide semiconductor layer is formed to a thickness of greater than or equal to 1 nm and less than or equal to 10 nm over the gate insulating layer 204. In this embodiment, the first oxide semiconductor layer is formed to a thickness of 5 nm in an oxygen atmosphere, an argon atmosphere, or a mixed atmosphere of argon and oxygen under such conditions that a target for an oxide semiconductor (a target for an In—Ga—Zn-based oxide semiconductor containing In₂O₃, Ga₂O₃, and ZnO at 1:1:2 [molar ratio]) is used, the distance between the substrate and the target is 170 mm, the substrate temperature is 250° C., the pressure is 0.4 Pa, and the direct current (DC) power is 0.5 kW.

Next, first heat treatment is performed by setting an atmosphere where the substrate is placed to a nitrogen atmosphere or dry air. The temperature of the first heat treatment is higher than or equal to 200° C. and lower than or equal to 450° C. In addition, heating time of the first heat treatment is longer than or equal to 1 hour and shorter than or equal to 24 hours. By the first heat treatment, a first crystalline oxide semiconductor layer 148 a is formed (see FIG. 11B).

Next, a second oxide semiconductor layer with a thickness of more than 10 nm is formed over the first crystalline oxide semiconductor layer 148 a. In this embodiment, the second oxide semiconductor layer is formed to a thickness of 25 nm by using a sputtering gas of oxygen, argon, or a mixture of argon and oxygen under such conditions that a target for an oxide semiconductor (a target for an In—Ga—Zn-based oxide semiconductor containing In₂O₃, Ga₂O₃, and ZnO at 1:1:2 [molar ratio]) is used; the distance between the substrate and the target is 170 mm; the substrate temperature is 400° C.; the pressure is 0.4 Pa; and the direct current (DC) power is 0.5 kW.

Then, second heat treatment is performed by setting an atmosphere where the substrate is placed to a nitrogen atmosphere or dry air. The temperature of the second heat treatment is higher than or equal to 200° C. and lower than or equal to 450° C. In addition, heating time of the second heat treatment is longer than or equal to 1 hour and shorter than or equal to 24 hours. By the second heat treatment, a second crystalline oxide semiconductor layer 148 b is formed (see FIG. 11C).

The following process is similar to that of Embodiment 1, that is, a source electrode 206 a, a drain electrode 206 b, an insulating layer 207, and the like are formed; and the insulating layer 207, the first crystalline oxide semiconductor layer 148 a, and the second crystalline oxide semiconductor layer 148 b are etched using the same resist mask, by which the number of photolithography steps is reduced.

Thus, in accordance with Embodiment 1, the transistor 111 can be obtained. Note that in the case of using this embodiment, the stacked layers of the first crystalline oxide semiconductor layer 148 a and the second crystalline oxide semiconductor layer 148 b form a semiconductor layer including a channel formation region of the transistor. The first crystalline oxide semiconductor layer 148 a and the second crystalline oxide semiconductor layer 148 b have c-axis alignment. Note that the first crystalline oxide semiconductor layer 148 a and the second crystalline oxide semiconductor layer 148 b include an oxide including a crystal with c-axis alignment (also referred to as C-Axis Aligned Crystal (also referred to as CAAC)), which has neither a single crystal structure nor an amorphous structure. The first crystalline oxide semiconductor layer 148 a and the second crystalline oxide semiconductor layer 148 b partly include a crystal grain boundary.

In order to obtain the CAAC, it is important to form hexagonal crystal in an initial stage of deposition of an oxide semiconductor film and cause crystal growth from the hexagonal crystal as a seed crystal. The substrate heating temperature is higher than or equal to 100° C. and lower than or equal to 500° C., preferably higher than or equal to 200° C. and lower than or equal to 400° C., further preferably higher than or equal to 250° C. and lower than or equal to 300° C. In addition to this, by performing heat treatment on the deposited oxide semiconductor film at a temperature higher than the substrate heating temperature at the deposition, microdefects in the film and defects at the interface of a stacked layer can be repaired.

In the case of the transistor including stacked layers of the first crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer, the amount of change in threshold voltage of the transistor between before and after being irradiated with light or being subjected to a bias-temperature (BT) stress test can be reduced; thus, such a transistor has stable electrical characteristics.

This embodiment can be freely combined with any of the other embodiments.

Embodiment 3

One mode of a display device in which any of the transistors described in Embodiment 1 and Embodiment 2 is used is illustrated in FIGS. 12A and 12B.

FIG. 12A is a plan view of a panel in which a transistor 4010 and a liquid crystal element 4013 are sealed between a first substrate 4001 and a second substrate 4006 with a sealant 4005. FIG. 12B is a cross-sectional view taken along line M-N in FIG. 12A. A groove portion 4040 is provided over the first substrate 4001.

The sealant 4005 is provided so as to surround a pixel portion 4002 provided over the first substrate 4001. The second substrate 4006 is provided over the pixel portion 4002. Accordingly, the pixel portion 4002 is sealed together with a liquid crystal layer 4008 by the first substrate 4001, the sealant 4005, and the second substrate 4006.

Further, an input terminal 4020 is provided in a region over the first substrate 4001 outside a region surrounded by the sealant 4005, and flexible printed circuits (FPCs) 4018 a and 4018 b are connected to the input terminal 4020. The FPC 4018 a is electrically connected to a signal line driver circuit 4003 which is separately provided over another substrate, and the FPC 4018 b is electrically connected to a scan line driver circuit 4004 which is separately provided over another substrate. Various signals and potentials supplied to the pixel portion 4002 are supplied from the signal line driver circuit 4003 and the scan line driver circuit 4004 via the FPC 4018 a and the FPC 4018 b.

Note that a connection method of separately formed driver circuits is not particularly limited, and a chip on glass (COG) method, a wire bonding method, a tape carrier package (TCP) method, a tape automated bonding (TAB) method, or the like can be used.

Although not shown, the signal line driver circuit 4003 or the scan line driver circuit 4004 may be provided over the substrate 4001 with the use of the transistor disclosed in this specification.

As a display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element) can be used. Furthermore, a display medium whose contrast is changed by an electric effect, such as electronic ink, can be used.

The display device illustrated in FIGS. 12A and 12B includes an electrode 4015 and a wiring 4016. The electrode 4015 and the wiring 4016 are electrically connected to a terminal included in the FPC 4018 a via an anisotropic conductive layer 4019.

The electrode 4015 is formed using the same conductive layer as a first electrode 4030, and the wiring 4016 is formed using the same conductive layer as a source and a drain electrode of the transistor 4010.

In this embodiment, any of the transistors described in Embodiment 1 and Embodiment 2 can be applied to the transistor 4010. The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element to form a display panel. A variety of display elements can be used for the display element as long as display can be performed.

FIGS. 12A and 12B illustrate an example of a display device in which a liquid crystal element is used as a display element. In FIGS. 12A and 12B, the liquid crystal element 4013 which is a display element includes the first electrode 4030, a second electrode 4031, and the liquid crystal layer 4008. Note that insulating layers 4032 and 4033 serving as alignment films are provided so that the liquid crystal layer 4008 is provided therebetween. The insulating layer 4032 functioning as an alignment film is also provided over the groove portion 4040. The second electrode 4031 is formed on the second substrate 4006 side. The first electrode 4030 and the second electrode 4031 are stacked with the liquid crystal layer 4008 provided therebetween.

A spacer 4035 is a columnar spacer which is formed over the second substrate 4006 using an insulating layer and is provided to control the thickness of the liquid crystal layer 4008 (a cell gap). Alternatively, a spherical spacer may be used.

In the case where a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low-molecular liquid crystal, a high-molecular liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an anti-ferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on conditions.

Alternatively, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while temperature of cholesteric liquid crystal is increased. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which 5 wt. % or more of a chiral material is mixed is used for the liquid crystal layer in order to improve the temperature range. The liquid crystal composition which includes a liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less, and has optical isotropy, which makes the alignment process unneeded and viewing angle dependence small. In addition, since an alignment film does not need to be provided and rubbing treatment is unnecessary, electrostatic discharge damage caused by the rubbing treatment can be prevented and defects and damage of the liquid crystal display device can be reduced in the manufacturing process. Thus, productivity of the liquid crystal display device can be increased.

The specific resistivity of the liquid crystal material is higher than or equal to 1×10⁹ Ω·cm, preferably higher than or equal to 1×10¹¹ Ω·cm, more preferably higher than or equal to 1×10¹² Ω·cm. The value of the specific resistivity in this specification is measured at 20° C.

The size of storage capacitor formed in the liquid crystal display device is set considering the leakage current of the transistor provided in the pixel portion or the like so that electric charge can be held for a predetermined period. By using the transistor in which a purified oxide semiconductor is used for a semiconductor layer including a channel region, it is enough to provide a storage capacitor having capacitance that is less than or equal to ⅓, preferably less than or equal to ⅕ of liquid crystal capacitance of each pixel.

In the transistor used in this embodiment, including a purified oxide semiconductor layer, the current in an off state (the off-state current) can be made small. Accordingly, an electrical signal such as an image signal can be held for a longer period, and a writing interval can be set longer in an on state. Accordingly, frequency of refresh operation can be reduced, which leads to an effect of suppressing power consumption. In addition, in the transistor including a purified oxide semiconductor layer, a potential applied to the liquid crystal element can be held even when a storage capacitor is not provided.

The field-effect mobility of the transistor including a purified oxide semiconductor layer used in this embodiment can be relatively high, whereby high-speed operation is possible. Therefore, by using the transistor in a pixel portion of a liquid crystal display device, a high-quality image can be provided. In addition, since the transistors can be separately provided in a driver circuit portion and a pixel portion over one substrate, the number of components of the liquid crystal display device can be reduced.

For the liquid crystal display device, a twisted nematic (TN) mode, an in-plane-switching (IPS) mode, a fringe field switching (FFS) mode, an axially symmetric aligned micro-cell (ASM) mode, an optical compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, or the like can be used.

Further, a normally black liquid crystal display device such as a transmissive liquid crystal display device utilizing a vertical alignment (VA) mode may also be used. Here, the vertical alignment mode is a method of controlling alignment of liquid crystal molecules of a liquid crystal display panel, in which liquid crystal molecules are aligned vertically to a panel surface when no voltage is applied. Some examples are given as the vertical alignment mode. For example, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an advanced super view (ASV) mode, and the like can be used. Moreover, it is possible to use a method called domain multiplication or multi-domain design, in which a pixel is divided into some regions (subpixels) and molecules are aligned in different directions in their respective regions.

In the liquid crystal display device, a black matrix (a light-blocking layer); an optical member (an optical substrate) such as a polarizing member, a retardation member, or an anti-reflection member; and the like are provided as appropriate. For example, circular polarization may be obtained by using a polarizing substrate and a retardation substrate. In addition, a backlight, a side light, or the like may be used as a light source.

In addition, it is possible to employ a time-division display method (also called a field-sequential driving method) with the use of a plurality of light-emitting diodes (LEDs) as a backlight. By employing a field-sequential driving method, color display can be performed without using a color filter.

As a display method in the pixel portion, a progressive method, an interlace method or the like can be employed. Further, color elements controlled in a pixel at the time of color display are not limited to three colors: R, and B (R, G, and B correspond to red, green, and blue, respectively). For example, R, G, B, and W (W corresponds to white); R, B, and one or more of yellow, cyan, magenta, and the like; or the like can be used. Further, the sizes of display regions may be different between respective dots of color elements. However, one embodiment of the present invention is not limited to a liquid crystal display device for color display and can be applied to a liquid crystal display device for monochrome display.

In FIGS. 12A and 12B, a flexible substrate as well as a glass substrate can be used as any of the first substrate 4001 and the second substrate 4006. For example, a light-transmitting plastic substrate or the like can be used. As plastic, a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film can be used. In addition, a sheet with a structure in which an aluminum foil is sandwiched between PVF films or polyester films can be used.

The liquid crystal display device displays an image by transmitting light from a light source or a display element. Therefore, the substrate and the thin films such as the insulating layer and the conductive layer provided for the pixel portion where light is transmitted have light-transmitting properties with respect to light in the visible-light wavelength range.

The first electrode and the second electrode (each of which may be called a pixel electrode, a common electrode, an opposite electrode, or the like) for applying voltage to the display element may have light-transmitting properties or light-reflecting properties, which depends on the direction in which light is extracted, the position where the electrode is provided, and the pattern structure of the electrode.

Any of the first electrode 4030 and the second electrode 4031 can be formed using a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added. Alternatively, a material including one to ten graphene sheets may be used.

One of the first electrode 4030 and the second electrode 4031 can be formed using one or plural kinds of materials selected from metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag); alloys of these metals; and nitrides of these metals.

A conductive composition including a conductive high molecule (also referred to as a conductive polymer) can be used for the first electrode 4030 and the second electrode 4031. As the conductive high molecule a so-called π-electron conjugated conductive high molecule can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, and a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.

Further, since a transistor is easily broken by static electricity or the like, a protection circuit is preferably provided. The protection circuit is preferably formed using a non-linear element.

As described above, by using any of the transistors described in Embodiment 1 and Embodiment 2, a liquid crystal display device with high reliability can be provided. Note that the transistors described in Embodiment 1 and Embodiment 2 can be applied to not only semiconductor devices having the display functions described above but also semiconductor devices having a variety of functions, such as a power device which is mounted on a power supply circuit, a semiconductor integrated circuit such as LSI, and a semiconductor device having an image sensor function of reading information of an object.

This embodiment can be freely combined with any of the other embodiments.

Embodiment 4

In this embodiment, with the use of a display device which switches between an image for a left eye and an image for a right eye at high speed, an example in which a 3D image which is a moving image or a still image is seen with dedicated glasses with which videos of the display device are synchronized will be described with reference to FIGS. 13A and 13B.

FIG. 13A illustrates an external view in which a display device 2711 and dedicated glasses 2701 are connected to each other with a cable 2703. The liquid crystal display device disclosed in this specification can be used as the display device 2711. In the dedicated glasses 2701, shutters provided in a panel 2702 a for a left eye and a panel 2702 b for a right eye are alternately opened and closed, whereby a user can see an image of the display device 2711 as a 3D image.

In addition, FIG. 13B is a block diagram illustrating a main structure of the display device 2711 and the dedicated glasses 2701.

The display device 2711 illustrated in FIG. 13B includes a display control circuit 2716, a display portion 2717, a timing generator 2713, a source line driver circuit 2718, an external operation unit 2722, and a gate line driver circuit 2719. Note that an output signal changes in accordance with operation by the external operation unit 2722 such as a keyboard.

In the timing generator 2713, a start pulse signal and the like are formed, and a signal for synchronizing an image for a left eye and the shutter of the panel 2702 a for a left eye, a signal for synchronizing an image for a right eye and the shutter of the panel 2702 b for a right eye, and the like are formed.

A synchronization signal 2731 a of the image for a left eye is input to the display control circuit 2716, so that the image for a left eye is displayed on the display portion 2717. At the same time, a synchronization signal 2730 a for opening the shutter of the panel 2702 a for a left eye is input to the panel 2702 a for a left eye. In addition, a synchronization signal 2731 b of the image for a right eye is input to the display control circuit 2716, so that the image for a right eye is displayed on the display portion 2717. At the same time, a synchronization signal 2730 b for opening the shutter of the panel 2702 b for a right eye is input to the panel 2702 b for a right eye.

Since switching between an image for a left eye and an image for a right eye is performed at high speed, the display device 2711 preferably employs a successive color mixing method (a field sequential method) in which color display is performed by time division with use of light-emitting diodes (LEDs).

Further, since a field sequential method is employed, it is preferable that the timing generator 2713 input signals that synchronize with the synchronization signals 2730 a and 2730 b to the backlight portion of the light-emitting diodes. Note that the backlight portion includes LEDs of R, and B colors.

This embodiment can be freely combined with any of the other embodiments in this specification.

Embodiment 5

In this embodiment, examples of electronic appliances each including the display device described in the above embodiment will be described.

FIG. 14A illustrates a laptop personal computer, which includes a main body 3001, a housing 3002, a display portion 3003, a keyboard 3004, and the like. By using the liquid crystal display device described in the above embodiment, a highly reliable laptop personal computer can be obtained.

FIG. 14B is a personal digital assistant (PDA) which includes a main body 3021 provided with a display portion 3023, an external interface 3025, operation buttons 3024, and the like. A stylus 3022 is included as an accessory for operation. By using the liquid crystal display device described in the above embodiment, a highly reliable personal digital assistant (PDA) can be obtained.

FIG. 14C illustrates an example of an e-book reader. For example, the e-book reader includes two housings, a housing 2706 and a housing 2704. The housing 2706 is combined with the housing 2704 by a hinge 2712, so that the e-book reader can be opened and closed using the hinge 2712 as an axis. With such a structure, the e-book reader can operate like a paper book.

A display portion 2705 and a display portion 2707 are incorporated in the housing 2706 and the housing 2704, respectively. The display portion 2705 and the display portion 2707 may display a continuous image or different images. In the structure where different images are displayed on different display portions, for example, the right display portion (the display portion 2705 in FIG. 14C) displays text and the left display portion (the display portion 2707 in FIG. 14C) displays graphics. By using the liquid crystal display device described in the above embodiment, a highly reliable e-book reader can be obtained.

FIG. 14C illustrates an example in which the housing 2706 is provided with an operation portion and the like. For example, the housing 2706 is provided with a power supply terminal 2721, operation keys 2723, a speaker 2725, and the like. With the operation keys 2723, pages can be turned. Note that a keyboard, a pointing device, or the like may also be provided on the surface of the housing, on which the display portion is provided. Furthermore, an external connection terminal (an earphone terminal, a USB terminal, or the like), a recording medium insertion portion, and the like may be provided on the back surface or the side surface of the housing. Further, the e-book reader may have a function of an electronic dictionary.

The e-book reader may transmit and receive data wirelessly. Through wireless communication, desired book data or the like can be purchased and downloaded from an e-book server.

FIG. 14D illustrates a mobile phone, which includes two housings, a housing 2800 and a housing 2801. The housing 2801 includes a display panel 2802, a speaker 2803, a microphone 2804, a pointing device 2806, a camera lens 2807, an external connection terminal 2808, and the like. In addition, the housing 2800 includes a solar cell 2810 having a function of charge of the portable information terminal, an external memory slot 2811, and the like. Further, an antenna is incorporated in the housing 2801.

The display panel 2802 is provided with a touch screen. A plurality of operation keys 2805 which is displayed as images is illustrated by dashed lines in FIG. 14D. Note that a boosting circuit by which a voltage output from the solar cell 2810 is increased to be sufficiently high for each circuit is also included.

In the display panel 2802, the display direction can be appropriately changed depending on a usage pattern. Further, the mobile phone is provided with the camera lens 2807 on the same surface as the display panel 2802, and thus it can be used as a video phone. The speaker 2803 and the microphone 2804 can be used for videophone calls, recording and playing sound, and the like as well as voice calls. Moreover, the housings 2800 and 2801 in a state where they are developed as illustrated in FIG. 14D can shift by sliding so that one is lapped over the other; therefore, the size of the mobile phone can be reduced, which makes the mobile phone suitable for being carried.

The external connection terminal 2808 can be connected to an AC adapter and various types of cables such as a USB cable, and charging and data communication with a personal computer are possible. Moreover, a large amount of data can be stored by inserting a storage medium into the external memory slot 2811 and can be moved.

Further, in addition to the above functions, an infrared communication function, a television reception function, or the like may be provided. By using the liquid crystal display device described in the above embodiment, a highly reliable mobile phone can be provided.

FIG. 14E illustrates a digital video camera which includes a main body 3051, a display portion A 3057, an eyepiece 3053, an operation switch 3054, a display portion B 3055, a battery 3056, and the like. By using the liquid crystal display device described in the above embodiment, a highly reliable digital video camera can be provided.

FIG. 14F illustrates an example of a television set. In the television set, a display portion 9603 is incorporated in a housing 9601. The display portion 9603 can display images. Here, the housing 9601 is supported by a stand 9605. By using the liquid crystal display device described in the above embodiment, a highly reliable television set can be provided.

The television set can be operated by an operation switch of the housing 9601 or a separate remote controller. Further, the remote controller may be provided with a display portion for displaying data output from the remote controller.

Note that the television set is provided with a receiver, a modem, and the like. With the use of the receiver, general television broadcasting can be received. Moreover, when the television set is connected to a communication network with or without wires via the modem, one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers) information communication can be performed.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

Example 1

A liquid crystal display device was manufactured through four photolithography steps using a method disclosed in the above embodiment. In this example, a stacked structure of a groove portion in a liquid crystal display device manufactured through four photolithography steps will be described with reference to FIGS. 19A and 19B. FIG. 19A is a cross-sectional transmission electron microscopy (TEM) image showing a stacked structure of a groove portion, which corresponds to the cross section of a portion indicated by a chain line H1-H2 in FIG. 1. FIG. 19B is a schematic view of FIG. 19A for easy understanding of the TEM image of FIG. 19A. A scale bar with 0.3-μm increments is displayed in the lower left of FIGS. 19A and 19B.

In the cross section H1-H2 in FIGS. 19A and 19B, a silicon nitride layer as a base layer 901 a and a silicon oxynitride layer as a base layer 901 b were formed over a glass substrate 900. Over the base layer 901 b, a silicon oxynitride layer was formed as a gate insulating layer 904, and then an In—Ga—Zn-based oxide semiconductor was deposited as a semiconductor layer 905 over the gate insulating layer 904. Then, as a wiring layer 916 over the semiconductor layer 905, four layers of a W layer, a Ti layer, an Al layer, and a Ti layer were formed to be stacked. A silicon oxide layer as an insulating layer 907 was formed over the semiconductor layer 905 and the wiring 916, and a silicon oxynitride layer as an insulating layer 908 was formed over the insulating layer 907.

A groove portion 930 was formed in such a manner that a resist mask was formed by a photolithography step, the insulating layer 908, the insulating layer 907, the semiconductor layer 905, the gate insulating layer 904, the base layer 901 b, and the base layer 901 a were selectively removed by an ICP etching method, and the resist mask was removed. In this example, part of the glass substrate 900 is also removed at the time of formation of the groove portion 930.

Then, a pixel electrode not illustrated in FIGS. 19A and 19B was formed, and an alignment film 911 was formed over the pixel electrode. From FIGS. 19A and 19B, it is found that the alignment film 911 remains also in the groove portion 930 and covers a side surface of the groove portion 930.

Note that a protective layer 921 and a protective layer 922 are layers formed over the sample for pretreatment for obtaining the cross-sectional TEM image.

By removing the semiconductor layer 905 in the groove portion 930 in this manner, formation of a parasitic transistor was able to be prevented, and further the liquid crystal display device was able to be manufactured with a smaller number of photolithography steps.

EXPLANATION OF REFERENCE

100: semiconductor device, 101: substrate, 102: pixel region, 103: terminal portion, 104: terminal portion, 105: terminal, 106: terminal, 107: terminal, 110: pixel, 111: transistor, 112: liquid crystal element, 113: capacitor, 114: electrode, 120: pixel, 130: pixel, 200: substrate, 201: base layer, 202: gate electrode, 203: wiring, 204: gate insulating layer, 205: semiconductor layer, 207: insulating layer, 208: contact hole, 210: pixel electrode, 211: pixel electrode, 212: wiring, 216: wiring, 219: contact hole, 220: contact hole, 221: electrode, 222: electrode, 230: groove portion, 231: edge, 232: edge, 233: edge, 234: edge, 240: groove portion, 251: groove portion, 252: groove portion, 253: groove portion, 254: groove portion, 255: groove portion, 256: groove portion, 257: groove portion, 258: groove portion, 900: glass substrate, 904: gate insulating layer, 905: semiconductor layer, 907: insulating layer, 908: insulating layer, 911: alignment film, 916: wiring, 921: protective layer, 922: protective layer, 930: groove portion, 2701: glasses, 2706: housing, 2703: cable, 2704: housing, 2705: display portion, 2707: display portion, 2711: display device, 2712: hinge, 2713: timing generator, 2716: display control circuit, 2717: display portion, 2718: source line driver circuit, 2719: gate line driver circuit, 2721: power supply terminal, 2722: external operation unit, 2723: operation keys, 2725: speaker, 2800: housing, 2801: housing, 2802: display panel, 2803: speaker, 2804: microphone, 2805: operation keys, 2806: pointing device, 2807: camera lens, 2808: external connection terminal, 2810: solar cell, 2811: external memory slot, 3001: main body, 3002: housing, 3003: display portion, 3004: keyboard, 3021: main body, 3022: stylus, 3023: display portion, 3024: operation buttons, 3025: external interface, 3051: main body, 3053: eyepiece, 3054: operation switch, 3055: display portion(B), 3056: battery, 3057: display portion(A), 4001: substrate, 4002: pixel portion, 4003: signal line driver circuit, 4004: scan line driver circuit, 4005: sealant, 4006: substrate, 4008: liquid crystal layer, 4010: transistor, 4013: liquid crystal element, 4015: electrode, 4016: wiring, 4018: FPC, 4019: anisotropic conductive layer, 4020: input terminal, 4030: electrode, 4031: electrode, 4032: insulating layer, 4035: spacer, 4040: groove portion, 9601: housing, 9603: display portion, 9605: stand, 148 a: crystalline oxide semiconductor layer, 148 b: crystalline oxide semiconductor layer, 206 a: source electrode, 206 b: drain electrode, 901 a: base layer, 901 b: base layer, 2702 a: panel for a left eye, 2702 b: panel for a right eye, 2730 a: synchronization signal, 2730 b: synchronization signal, 2731 a: synchronization signal, 2731 b: synchronization signal, 4018 a: FPC, and 4018 b: FPC.

This application is based on Japanese Patent Application serial no. 2010-207164 filed with Japan Patent Office on Sep. 15, 2010, the entire contents of which are hereby incorporated by reference. 

1. A display device comprising: a transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer; a first wiring electrically connected to the gate electrode; a second wiring electrically connected to one of the source electrode and the drain electrode; a pixel electrode electrically connected to the other of the source electrode and the drain electrode; a capacitor wiring; a first groove portion in the semiconductor layer; and a second groove portion in the semiconductor layer, wherein the semiconductor layer overlaps with the first wiring, the second wiring, the pixel electrode, and the capacitor wiring, wherein the first groove portion is formed over the first wiring to cross the first wiring in a line width direction of the first wiring, wherein the second groove portion is formed over the capacitor wiring to cross the capacitor wiring in a line width direction of the capacitor wiring, and wherein the second groove portion extends beyond edges of the pixel electrode in a direction parallel to a direction in which the second wiring extends.
 2. The display device according to claim 1, wherein the semiconductor layer does not exist on bottom surfaces of the first groove portion and the second groove portion.
 3. The display device according to claim 1, wherein the semiconductor layer exists on side surfaces of the first groove portion and the second groove portion.
 4. The display device according to claim 1, wherein the first groove portion and the second groove portion overlaps with an alignment film.
 5. The display device according to claim 1, wherein at least a part of the second groove portion overlaps with the pixel electrode.
 6. The display device according to claim 1, wherein the second groove portion and the pixel electrode are spaced with each other.
 7. The display device according to claim 1, wherein the semiconductor layer includes an oxide semiconductor.
 8. A display device comprising: a transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer; a first wiring electrically connected to the gate electrode; a second wiring electrically connected to one of the source electrode and the drain electrode; a pixel electrode electrically connected to the other of the source electrode and the drain electrode; a capacitor wiring; and a groove portion in the semiconductor layer, wherein the semiconductor layer overlaps with the first wiring, the second wiring, the pixel electrode, and the capacitor wiring, wherein the groove portion is formed over the first wiring to cross the first wiring in a line width direction of the first wiring, wherein the groove portion is formed over the capacitor wiring to cross the capacitor wiring in a line width direction of the capacitor wiring, and wherein the groove portion extends beyond edges of the pixel electrode in a direction parallel to a direction in which the second wiring extends.
 9. The display device according to claim 8, wherein the semiconductor layer does not exist on a bottom surface of the groove portion.
 10. The display device according to claim 8, wherein the semiconductor layer exists on a side surface of the groove portion.
 11. The display device according to claim 8, wherein the groove portion overlaps with an alignment film.
 12. The display device according to claim 8, wherein at least a part of the groove portion overlaps with the pixel electrode.
 13. The display device according to claim 8, wherein the groove portion and the pixel electrode are spaced with each other.
 14. The display device according to claim 8, wherein the semiconductor layer includes an oxide semiconductor.
 15. A display device comprising: a transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer; a first wiring electrically connected to the gate electrode; a second wiring electrically connected to one of the source electrode and the drain electrode; a pixel electrode electrically connected to the other of the source electrode and the drain electrode; a capacitor wiring; a first groove portion in the semiconductor layer; a second groove portion in the semiconductor layer; and a third groove portion in the semiconductor layer, wherein the semiconductor layer overlaps with the first wiring, the second wiring, the pixel electrode, and the capacitor wiring, wherein the first groove portion is formed over the first wiring to cross the first wiring in a line width direction of the first wiring, wherein the second groove portion is formed over the capacitor wiring to cross the capacitor wiring in a line width direction of the capacitor wiring, and wherein the third groove portion extends beyond edges of the pixel electrode in a direction parallel to a direction in which the second wiring extends.
 16. The display device according to claim 15, wherein the semiconductor layer does not exist on bottom surfaces of the first groove portion, the second groove portion, and the third groove portion.
 17. The display device according to claim 15, wherein the semiconductor layer exists on side surfaces of the first groove portion, the second groove portion, and the third groove portion.
 18. The display device according to claim 15, wherein the third groove portion overlaps with an alignment film.
 19. The display device according to claim 15, wherein at least a part of the third groove portion overlaps with the pixel electrode.
 20. The display device according to claim 15, wherein the second groove portion and the pixel electrode are spaced with each other.
 21. The display device according to claim 15, wherein the semiconductor layer includes an oxide semiconductor.
 22. A manufacturing method of a display device, comprising the steps of: forming a gate electrode over a substrate by a first photolithography step; forming a gate insulating layer over the gate electrode; forming a semiconductor layer over the gate insulating layer; forming a source electrode and a drain electrode over the semiconductor layer by a second photolithography step; forming an insulating layer over the source electrode and the drain electrode; removing a part of the insulating layer overlapping with the drain electrode to form a contact hole by a third photolithography step, removing another part of the insulating layer, a part of the semiconductor layer, and a part of the gate insulating layer to form a groove portion by the third photolithography step, and forming a pixel electrode over the insulating layer by a fourth photolithography step.
 23. The manufacturing method of a display device according to claim 22, wherein a base layer is formed between the substrate and the gate electrode.
 24. The manufacturing method of a display device according to claim 22, wherein the semiconductor layer includes an oxide semiconductor.
 25. The manufacturing method of a display device according to claim 22, wherein the gate electrode, the source electrode, or the drain electrode includes a material including copper.
 26. The manufacturing method of a display device according to claim 25, wherein a maximum process temperature after formation of the gate electrode, the source electrode, or the drain electrode is 450° C. or lower.
 27. The manufacturing method of a display device according to claim 22, wherein the gate electrode, the source electrode, or the drain electrode includes a material including aluminum.
 28. The manufacturing method of a display device according to claim 27, wherein a maximum process temperature after formation of the gate electrode, the source electrode, or the drain electrode is 380° C. or lower. 